signal "L1"(L2,L3,R1,R2,R3)has multiple sources 该怎么解决？？

blake

signal "L1"(L2,L3,R1,R2,R3)has multiple sources 该怎么解决？？ [复制链接]

USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CONTROL IS
          PORT(S2,S1,S0: STD_LOGIC_VECTOR(3 DOWNTO 0);
                    CLK:IN STD_LOGIC;
      L1,L2,L3,R1,R2,R3:OUT STD_LOGIC);
END ENTITY CONTROL; 
            ARCHITECTURE CTRL OF CONTROL IS
            BEGIN
            PROCESS(S2,S1,S0,CLK)
            BEGIN
              IF(S2="0" AND S1="0" AND S0="0")THEN
              L1<='0';L2<='0';L3<='0';
              R1<='0';R2<='0';R3<='0';
            ELSIF CLK'EVENT AND CLK='1' THEN
             IF(S2="0" AND S1="0" AND S0="1")THEN
              L1<='1';L2<='0';L3<='0';
              R1<='0';R2<='0';R3<='0';
            ELSIF(S2="0" AND S1="1" AND S0="0")THEN
              L1<='0';L2<='0';L3<='0';
              R1<='1';R2<='0';R3<='0';
           END IF;
          END IF;
         END  PROCESS;
            PROCESS(S2,S1,S0)
            BEGIN
              IF(S2="0" AND S1="1" AND S0="1")THEN
              L1<='1';L2<='1';L3<='1';
              R1<='1';R2<='1';R3<='1';
           ELSIF(S2="1" AND S1="0" AND S0="0")THEN
              L1<='0';L2<='0';L3<='1';
              R1<='0';R2<='0';R3<='1';
           END IF;
         END  PROCESS;
       END  ARCHITECTURE CTRL;

eeleader

改变你的程序表达方法即可

lidonglei1

两个进程不能同时控制一个寄存器。。。。有可能出现同一时间一个进程让他高，一个进程让他低。。所以不成

eeleader

如果同时驱动，容易让芯片内部短路！

tx_xy

在两个process中 都有对L1的赋值处理 这是不允许的 修改下代码。

yangmingnwpu

在进程中不要直接对输出信号进行赋值，改用信号或变量。在所有进程之后，结构体结束之前，再将信号或变量赋值给输出信号。