always@(posedge clks or negedge clr)
begin
if(!clr) //清零信号,将计数清零
begin
s_high<=4'd0;
s_low<=4'd0;
cm<=4'd0;
end
else
begin
if(s_low==4'd9&&s_high<4'd5) //如果分秒低位等于9时
begin
s_high<=s_high+1;
s_low<=4'd0;
cm<=4'd0;
end
else if(s_low<4'd9&&s_high<=4'd5) //如果分秒低位小于9时
begin
s_high<=s_high;
s_low<=s_low+1;
cm<=4'd0;
end
else if(s_low==4'd9&&s_high==4'd5) //如果为59时,产生进位
begin
s_high<=4'd0;
s_low<=4'd0;
cm<=4'd1;
end
end
end
endmodule