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引用 9 楼 navi_dx 的回复:
Seven_zhangxw
OEMIdle看了一下,主要是修改PWM寄存器降频和恢复频率,如果升高频率,怎么处理外设的分频和锁频呢?比如UARTs的时钟
一般来说,系统一起来的时候默认就是最大频率了,这样,你就不能再升频率了。现在考虑的是如果现在是工作在低频率下,你还可以往上升,我贴一段代码你看看:
;------------------------------------------------------------------------------
; Clock Division Change funtion for DVS on S3C2440A.
;------------------------------------------------------------------------------
;UPLLVAL EQU (((56 << 12) + (2 << 4) + 2)) ; 48MHz,Fin=12Mhz
;==========================================================
;void DVS400MHz(void)
;==========================================================
LEAF_ENTRY DVS400MHz ;400Mhz, 1:3:6
ldr r0, = CLKDIVN
ldr r1, = 0x7 ;1:3:6
str r1, [r0]
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0x00ffffff
str r1, [r0]
; ldr r0, = UPLLCON ; Fin=12MHz, Fout=48MHz
; ldr r1, = UPLLVAL
; str r1, [r0]
nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
ldr r0, = MPLLCON ; Configure MPLL ; Fin=12MHz, Fout=50MHz
ldr r1, = 0x5c011 ;PLLVAL ;(((92 << 12) + (1 << 4) + 1)) ;Fin=12Mhz
str r1, [r0]
; delay
mov r0, #0x200
51 subs r0, r0, #1
bne %B51
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0x2 ; 1us for only change SDIV value
str r1, [r0]
mov pc, lr
;==========================================================
;void DVS266MHz(void)
;==========================================================
LEAF_ENTRY DVS266MHz ;266Mhz, 1:2:4
ldr r0, = CLKDIVN
ldr r1, = 0x03 ;1:2:4
str r1, [r0]
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0x00ffffff
str r1, [r0]
; ldr r0, = UPLLCON ; Fin=12MHz, Fout=48MHz
; ldr r1, = UPLLVAL
; str r1, [r0]
nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
ldr r0, = MPLLCON ; Configure MPLL ; Fin=12MHz, Fout=50MHz
ldr r1, = 0x76061 ;PLLVAL ;(((118 << 12) + (6 << 4) + 1))
str r1, [r0]
; delay
mov r0, #0x200
52 subs r0, r0, #1
bne %B52
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0x2 ; 1us for only change SDIV value
str r1, [r0]
mov pc, lr
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