Crossing clock domains - Signal

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Crossing clock domains - Signal [复制链接]

A signal to another clock domain

Let's say a signal from clkA domain is needed in clkB domain. It needs to be "synchronized" to clkB domain, so we want to build a "synchronizer" design, which takes a signal from clkA domain, and creates a new signal into clkB domain.

In this first design, we assume that the signal-in changes "slowly" compared to both clkA and clkB clock speeds.
Typically all you need to do is to use two flip-flops to move the signal from clkA to clkB (to learn why, get back to the links).

module Signal_CrossDomain(
    clkA, SignalIn, 
    clkB, SignalOut);

// clkA domain signals
input clkA;
input SignalIn;

// clkB domain signals
input clkB;
output SignalOut;

// Now let's transfer SignalIn into the clkB clock domain
// We use a two-stages shift-register to synchronize the signal
reg [1:0] SyncA_clkB;
always @(posedge clkB) SyncA_clkB[0] <= SignalIn;      // notice that we use clkB
always @(posedge clkB) SyncA_clkB[1] <= SyncA_clkB[0]; // notice that we use clkB

assign SignalOut = SyncA_clkB[1];  // new signal synchronized to (=ready to be used in) clkB domain
endmodule

The two flip-flops have the side-effect of delaying the signal.
For example, here are waveforms where you can see the slow moving signal being synchronized (and delayed) to clkB domain by the two flip-flops:

 

原汁原味的异步处理方法，参考上面的E文！