初学FPGA，帮我看下我的这个程序错在哪里了

yangyi1818

初学FPGA，帮我看下我的这个程序错在哪里了 [复制链接]

`timescale 1ns/1ns `include"addr3.v" module addr4; reg [3:0] a,b; reg cin; wire [3:0] sum; wire cout; integer i,j; addr3 add(sum,cout,a,b,cin); always #5 cin=~cin; initial begin a=0;b=0;cin=0; for(i=1;i<16;i=i+1) #10 a=i; end initial begin for(j=1;j<16;j=j+1) #10 b=i; end initial begin $monitor($time,,,"%d+%d+%b={%b.%d}",a,b,cin,cout,sum); #160 $finish; end endmodule

yangyi1818

`timescale 1ns/1ns
`include"addr3.v"
module addr4;
reg [3:0] a,b;
reg  cin;
wire [3:0] sum;
wire cout;
integer i,j;

addr3 add(sum,cout,a,b,cin);
always #5 cin=~cin;

initial
begin
a=0;b=0;cin=0;
for(i=1;i<16;i=i+1)
#10 a=i;
end

initial
begin
for(j=1;j<16;j=j+1)
#10 b=i;
end
initial
begin
$monitor($time,,,"%d+%d+%b={%b.%d}",a,b,cin,cout,sum);
#160 $finish;
end
endmodule

yangyi1818

module addr3(sum,cout,ina,inb,cin);
output [3:0] sum;
output cout;
input [3:0] ina,inb;
input cin;
assign
{cout,sum}=ina+inb+cin;
endmodule

jyl

用moedlsim仿真，没提示吗?

yangyi1818

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
        Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
        Info: Processing started: Tue Sep 22 13:32:13 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off addr4 -c addr4
Info: Found 2 design units, including 2 entities, in source file addr4.v
        Info: Found entity 1: addr3
        Info: Found entity 2: addr4
Info: Elaborating entity "addr4" for the top level hierarchy
Warning (10755): Verilog HDL warning at addr4.v(11): assignments to cin create a combinational loop
Warning (10230): Verilog HDL assignment warning at addr4.v(17): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at addr4.v(23): truncated value with size 32 to match size of target (4)
Warning (10855): Verilog HDL warning at addr4.v(21): initial value for variable b should be constant
Warning (10175): Verilog HDL warning at addr4.v(27): ignoring unsupported system task
Warning (10175): Verilog HDL warning at addr4.v(28): ignoring unsupported system task
Info: Elaborating entity "addr3" for hierarchy "addr3:add"
Warning: The following nets are missing source, defaulting to GND
        Warning (12110): Net "cin"
Error: Can't synthesize current design -- Top partition does not contain any logic
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 8 warnings
        Info: Allocated 133 megabytes of memory during processing
        Error: Processing ended: Tue Sep 22 13:32:15 2009
        Error: Elapsed time: 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 1 error, 8 warnings

qushaobo

Error: Can't synthesize current design -- Top partition does not contain any logic
testbench能被综合吗?

jyl

用modelsim编译通过，代码一般没什么问题的，是不是quartus使用有问题啊，设置top model了吗？

sadlife1000

:L !!!
JYL,modelsim 还能通过？
超级菜鸟啊啊啊！
一个问题，这不是C语言！十进制必须用'd数值格式来表示。
二个问题，第一个initial语句中b=i？何来i？
三个问题 $monitor系统函数 quartues不支持。
四个问题
   最严重的问题，adder4是testbench，波形测试文件，能综合吗？你要综合的问题是adder3。

yuji0boy

你的时钟信号，在alway之前因先赋值，cin=1'b0
你的应该是对一个全加器进行仿真吧。
感觉模块也有点乱，从开始学就要养成一些好的习惯，我也是刚学，碰到问题多改改吧。会有很大收获的。
你这个问题就让我有很多收获，我把你的程序稍稍改了下。你对比看看吧，我也是个学生，可能也有不对的地方，互相学习吧。
`timescale 1ns/1ns
`include"addr3.v"
module top;
    wire [3:0]a;
    wire [3:0]b;
    wire [3:0]sum;
    wire cout;
    wire cin;
    addr3 add(.sum(sum),.cout(cout),.ina(a),.inb(b),.cin(cin));
    add3_test add1(.a(a),.b(b),.cin(cin));
    initial
    begin
        $monitor($time,,,"%d+%d+%b=%b%d",a,b,cin,cout,sum);
        #160 $finish;
    end
endmodule


module add3_test(a,b,cin);
    output a,b,cin;
    reg cin;
    reg [3:0]a;
    reg [3:0]b;
    integer i,j;
    initial
        cin=1'b0;
    always #5 cin=~cin;
    initial
    begin
        a=0;
        b=0;
        for(i=1;i<16;i=i+1)
        #10 a=i;
    end
    initial
    begin
        for(j=1;j<16;j=j+1)
        #10 b=i;
    end
endmodule

skyyard

麻烦告诉一下，不可综合的该怎么操作了

eeleader

对于需要QUARTUS 综合的语句,FOR (I=1;I<16;I++) 这样语句是不能综合的!

eeleader-mcu

仿真一个加法器,有需要你这样写仿真语句的吗? 仿真语句仿真都有FOR  EVER  模拟信号,还有#60 等等延迟时间,你写的太复杂了!

常见泽1

恩 不可综合的还是蛮多的

EDA菜鸟

一个如此简单的程序搞得这么复杂啊。能不能把c和Verilog分开啊

eeleader

学FPGA， 了解FPGA框架，FPGA都是标准程序， if ----------else  语可以表达完成所有逻辑，而不需要那么多华而不实的表达！