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XMC4700 Relax 5V shield 评测:分析XMC4700 Easy Start Project [复制链接]

本帖最后由 qwerghf 于 2017-12-12 22:55 编辑

今天有空可以休息,继续开始玩转XMC4700,在上一节介绍了如何使用官方的IDE,本节开始使用官方的IDE来创建学习XMC4700。本次我们使用第一个工程选项创建工程,如下:

如上就是我们基于XMC4700创建Easy Start Project,根据以前开发的经验,我们先从系统时钟开始分析XMC4700工程。
对于M内核的MCU来说,都是先从汇编启动文件,然后跑到系统配置函数,系统时钟默认配置文件为system_XMC4700.c,如下所示


打开文件,根据硬件我们可以知道系统外部时钟源为12M晶振,可以从代码中看到
  1. /*
  2. //    <o> External crystal frequency [Hz]
  3. //       <8000000=> 8MHz
  4. //       <12000000=> 12MHz
  5. //       <16000000=> 16MHz
  6. //    <i> Defines external crystal frequency
  7. //    <i> Default: 8MHz
  8. */
  9. #define OSCHP_FREQUENCY (12000000U)

  10. /* USB PLL settings, fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz */
  11. /* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and fUSBPLLVCO <= 520 MHz*/
  12. #if OSCHP_FREQUENCY == 8000000U
  13. #define USB_PDIV (1U)
  14. #define USB_NDIV (95U)

  15. #elif OSCHP_FREQUENCY == 12000000U
  16. #define USB_PDIV (1U)
  17. #define USB_NDIV (63U)

  18. #elif OSCHP_FREQUENCY == 16000000U
  19. #define USB_PDIV (1U)
  20. #define USB_NDIV (47U)

  21. #else
  22. #error "External crystal frequency not supported"

  23. #endif
复制代码

可以看到系统时钟为12M,符合硬件,代码中也给我出8M和16M对应的配置定义。
系统的时钟配置函数如下:
  1. __WEAK void SystemInit(void)
  2. {
  3.   memcpy(g_chipid, CHIPID_LOC, 16);
  4.   
  5.   SystemCoreSetup();
  6.   SystemCoreClockSetup();
  7. }

  8. __WEAK void SystemCoreSetup(void)
  9. {
  10.   uint32_t temp;
  11.         
  12.   /* relocate vector table */
  13.   __disable_irq();
  14.   SCB->VTOR = (uint32_t)(&__Vectors);
  15.   __DSB();
  16.   __enable_irq();
  17.    
  18. #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
  19.   SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
  20.                  (3UL << 11*2)  );               /* set CP11 Full Access */
  21. #endif

  22.   /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
  23.   SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);

  24.   temp = FLASH0->FCON;
  25.   temp &= ~FLASH_FCON_WSPFLASH_Msk;
  26.   temp |= PMU_FLASH_WS;
  27.   FLASH0->FCON = temp;
  28. }
  29. __WEAK void SystemCoreClockSetup(void)
  30. {
  31. #if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
  32.   /* Enable factory calibration */
  33.   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
  34. #else
  35.   /* Automatic calibration uses the fSTDBY */

  36.   /* Enable HIB domain */
  37.   /* Power up HIB domain if and only if it is currently powered down */
  38.   if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
  39.   {
  40.     SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;

  41.     while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
  42.     {
  43.       /* wait until HIB domain is enabled */
  44.     }
  45.   }

  46.   /* Remove the reset only if HIB domain were in a state of reset */
  47.   if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
  48.   {
  49.     SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
  50.     delay(DELAY_CNT_150US_50MHZ);
  51.   }

  52. #if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
  53.   /* Enable OSC_ULP */
  54.   if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
  55.   {
  56.     /*enable OSC_ULP*/
  57.     while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
  58.     {
  59.       /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
  60.     }
  61.     SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;

  62.     /* Check if the clock is OK using OSCULP Oscillator Watchdog*/
  63.     while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
  64.     {
  65.       /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
  66.     }
  67.     SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;

  68.     /* wait till clock is stable */
  69.     do
  70.     {
  71.       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
  72.       {
  73.         /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
  74.       }
  75.       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;

  76.       delay(DELAY_CNT_50US_50MHZ);

  77.     } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);

  78.   }

  79.   /* now OSC_ULP is running and can be used*/
  80.   /* Select OSC_ULP as the clock source for RTC and STDBY*/
  81.   while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
  82.   {
  83.     /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
  84.   }
  85.   SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
  86. #endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */

  87.   /* Enable automatic calibration of internal fast oscillator */
  88.   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
  89. #endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */

  90.   delay(DELAY_CNT_50US_50MHZ);

  91. #if ENABLE_PLL

  92.   /* enable PLL */
  93.   SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);

  94. #if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
  95.   /* enable OSC_HP */
  96.   if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
  97.   {
  98.     SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
  99.     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;

  100.     /* select OSC_HP clock as PLL input */
  101.     SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;

  102.     /* restart OSC Watchdog */
  103.     SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;

  104.     while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
  105.     {
  106.       /* wait till OSC_HP output frequency is usable */
  107.     }   
  108.   }
  109. #else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */

  110.   /* select backup clock as PLL input */
  111.   SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
  112. #endif

  113.   /* Go to bypass the Main PLL */
  114.   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;

  115.   /* disconnect Oscillator from PLL */
  116.   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;

  117.   /* Setup divider settings for main PLL */
  118.   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
  119.                       (PLL_K2DIV_24MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
  120.                       (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));

  121.   /* Set OSCDISCDIS */
  122.   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;

  123.   /* connect Oscillator to PLL */
  124.   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;

  125.   /* restart PLL Lock detection */
  126.   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;

  127.   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
  128.   {
  129.     /* wait for PLL Lock at 24MHz*/
  130.   }

  131.   /* Disable bypass- put PLL clock back */
  132.   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
  133.   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
  134.   {
  135.     /* wait for normal mode */
  136.   }
  137. #endif /* ENABLE_PLL */

  138.   /* Before scaling to final frequency we need to setup the clock dividers */
  139.   SCU_CLK->SYSCLKCR = __SYSCLKCR;
  140.   SCU_CLK->PBCLKCR = __PBCLKCR;
  141.   SCU_CLK->CPUCLKCR = __CPUCLKCR;
  142.   SCU_CLK->CCUCLKCR = __CCUCLKCR;
  143.   SCU_CLK->WDTCLKCR = __WDTCLKCR;
  144.   SCU_CLK->EBUCLKCR = __EBUCLKCR;
  145.   SCU_CLK->USBCLKCR = __USBCLKCR | USB_DIV;
  146.   SCU_CLK->EXTCLKCR = __EXTCLKCR;

  147. #if ENABLE_PLL
  148.   /* PLL frequency stepping...*/
  149.   /* Reset OSCDISCDIS */
  150.   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;

  151.   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
  152.                           (PLL_K2DIV_48MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
  153.                           (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));

  154.   delay(DELAY_CNT_50US_48MHZ);

  155.   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
  156.                           (PLL_K2DIV_72MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
  157.                           (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));

  158.   delay(DELAY_CNT_50US_72MHZ);

  159.   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
  160.                           (PLL_K2DIV_96MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
  161.                           (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));

  162.   delay(DELAY_CNT_50US_96MHZ);

  163.   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
  164.                           (PLL_K2DIV_120MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
  165.                           (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));

  166.   delay(DELAY_CNT_50US_120MHZ);

  167.   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
  168.                           (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
  169.                           (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));

  170.   delay(DELAY_CNT_50US_144MHZ);

  171. #endif /* ENABLE_PLL */

  172. #if ENABLE_USBPLL
  173.   /* enable USB PLL first */
  174.   SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);

  175.   /* USB PLL uses as clock input the OSC_HP */
  176.   /* check and if not already running enable OSC_HP */
  177.   if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
  178.   {
  179.     /* check if Main PLL is switched on for OSC WDG*/
  180.     if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
  181.     {
  182.       /* enable PLL first */
  183.       SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
  184.     }

  185.     SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
  186.     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;

  187.     /* restart OSC Watchdog */
  188.     SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;

  189.     while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
  190.     {
  191.       /* wait till OSC_HP output frequency is usable */
  192.     }
  193.   }


  194.   /* Setup USB PLL */
  195.   /* Go to bypass the USB PLL */
  196.   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;

  197.   /* disconnect Oscillator from USB PLL */
  198.   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;

  199.   /* Setup Divider settings for USB PLL */
  200.   SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
  201.                         (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));

  202.   /* Set OSCDISCDIS */
  203.   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;

  204.   /* connect Oscillator to USB PLL */
  205.   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;

  206.   /* restart PLL Lock detection */
  207.   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;

  208.   while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
  209.   {
  210.     /* wait for PLL Lock */
  211.   }  
  212. #endif


  213.   /* Enable selected clocks */
  214.   SCU_CLK->CLKSET = __CLKSET;

  215. #if __EXTCLKPIN != 0
  216. #if __EXTCLKPIN == EXTCLK_PIN_P1_15
  217.   /* P1.15 */
  218.   PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
  219.   PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
  220. #else
  221.   /* P0.8 */
  222.   PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
  223.   PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
  224.   PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
  225. #endif
  226. #endif  /* ENABLE_EXTCLK == 1  */

  227.   SystemCoreClockUpdate();
  228. }

  229. __WEAK void SystemCoreClockUpdate(void)
  230. {
  231.   uint32_t pdiv;
  232.   uint32_t ndiv;
  233.   uint32_t kdiv;
  234.   uint32_t temp;

  235.   if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
  236.   {
  237.     /* fPLL is clock source for fSYS */
  238.     if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
  239.     {
  240.       /* PLL input clock is the backup clock (fOFI) */
  241.       temp = OFI_FREQUENCY;
  242.     }
  243.     else
  244.     {
  245.       /* PLL input clock is the high performance osicllator (fOSCHP) */
  246.       temp = OSCHP_GetFrequency();
  247.     }

  248.     /* check if PLL is locked */
  249.     if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
  250.     {
  251.       /* PLL normal mode */
  252.       /* read back divider settings */
  253.       pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
  254.       ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
  255.       kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;

  256.       temp = (temp / (pdiv * kdiv)) * ndiv;
  257.     }
  258.     else
  259.     {
  260.       /* PLL prescalar mode */
  261.       /* read back divider settings */
  262.       kdiv  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;

  263.       temp = (temp / kdiv);
  264.     }
  265.   }
  266.   else
  267.   {
  268.     /* fOFI is clock source for fSYS */   
  269.     temp = OFI_FREQUENCY;
  270.   }

  271.   temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
  272.   temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);

  273.   SystemCoreClock = temp;
  274. }

复制代码

从上述代码可以看出系统的时钟配置,具体配置的信息如下:
/*
//    Clock tree
//         System clock source selection
//                      <0=> fOFI
//                      <1=> fPLL
//                      Default: fPLL
//         System clock divider <1-256><#-1>
//                      Default: 2
//         CPU clock divider
//                      <0=> fCPU = fSYS
//                      <1=> fCPU = fSYS / 2
//                      Default: fCPU = fSYS
//          Peripheral clock divider
//                      <0=> fPB = fCPU
//                      <1=> fPB = fCPU / 2
//                      Default: fPB = fCPU
//          CCU clock divider
//                      <0=> fCCU = fCPU
//                      <1=> fCCU = fCPU / 2
//                      Default: fCCU = fCPU
//         Enable WDT clock
//             WDT clock source <0=> fOFI
//                                          <1=> fSTDBY
//                                          <2=> fPLL
//                      Default: fOFI
//             WDT clock divider <1-256><#-1>
//                      Default: 1
//        
//         Enable EBU clock
//               EBU clock divider  <1-64><#-1>
//             Default: 4
//        
//         Enable ETH clock
//        
//         Enable MMC clock
//        
//         Enable USB clock
//             USB clock source <0=> fUSBPLL
//                                      <1=> fPLL
//             Default: fPLL
//        
//         Enable external clock
//             External Clock Source Selection
//                  <0=> fSYS
//                  <2=> fUSB
//                  <3=> fPLL
//                   Default: fPLL
//             External Clock divider <1-512><#-1>
//                   Default: 288
//                   Only valid for USB PLL and PLL clocks
//             External Clock Pin Selection
//                  <0=> Disabled
//                  <1=> P0.8
//                  <2=> P1.15
//                   Default: Disabled
//        
//   


接下来分析main函数程序
  1. int main(void)
  2. {
  3.         /* Setup the system timer to tick every 100us */
  4.         SysTick_Config(SystemCoreClock / TICKS_PER_SECOND);

  5.         /* Configure P3.9 (LED) */
  6.         // P3.9 is used as GPIO for LED indication. Macros can be find in GPIO.h
  7.         P5_9_set_mode(OUTPUT_PP_GP);
  8.         P5_9_set_driver_strength(STRONG);
  9.         P5_9_reset();

  10.         /* Initialize and start ADC */
  11.         ADC0_Init();

  12.         /* Infinite loop */
  13.         for(;;){
  14.                 do{
  15.                         adc_result =  VADC_G0->RES[1];
  16.                 } while (!(adc_result >> VADC_G_RES_VF_Pos));
  17.                                         // wait until ADC result register 0 value is valid
  18.                                         // VADC.G0RES1.VF = 1: Valid Flag
  19.                                         // Indicates a new result in bitfield RESULT or bit FCR.
  20.                                         // 1B = Bitfield RESULT has been updated with new
  21.                                         // result value and has not yet been read, or bit
  22.                                         // FCR has been updated

  23.                 adc_result &= 0xFFF;           // mask ADC result
  24.                 Delay100US((adc_result << 1) + 500);
  25.                                        // tune minimum and maximum flashing time

  26.                 P5_9_toggle();
  27.                                        // toggle P3.9 (toggle LED) using GPIO.h macros
  28.         }
  29.         return 0;
  30. }
复制代码
先配置系统SysTick为100us中断一次,配置引脚5.9为输出引脚,引脚输出为强输出,先输出为低电平。然后初始化ADC0,并且启动ADC0转换。在while循环中,读取ADC转换的数据,用来产生延时的基数,翻转点灯。

对于DAVE的IDE发现有几个很好的功能,没有实际编译的代码为黑色背景,这样方便我们分析代码。

智能提醒,直接把鼠标停在代码上面,自动给出代码定义,比iar和mdk好很多,不需要再用第三方编辑器看代码。

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