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#ifndef __MSP430G2553
#define __MSP430G2553
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif
#if (((__TID__ >> 8) & 0x7F) != 0x2b)
#error msp430g2553.h file for use with ICC430/A430 only
#endif
#ifdef __IAR_SYSTEMS_ICC__
#include "in430.h"
#pragma language=extended
#define DEFC(name, address) __no_init volatile unsigned char name @ address;
#define DEFW(name, address) __no_init volatile unsigned short name @ address;
#define DEFXC volatile unsigned char
#define DEFXW volatile unsigned short
#endif
#ifdef __IAR_SYSTEMS_ASM__
#define DEFC(name, address) sfrb name = address;
#define DEFW(name, address) sfrw name = address;
#endif
#ifdef __cplusplus
#define READ_ONLY
#else
#define READ_ONLY const
#endif
#define BIT0 (0x0001u)
#define BIT1 (0x0002u)
#define BIT2 (0x0004u)
#define BIT3 (0x0008u)
#define BIT4 (0x0010u)
#define BIT5 (0x0020u)
#define BIT6 (0x0040u)
#define BIT7 (0x0080u)
#define BIT8 (0x0100u)
#define BIT9 (0x0200u)
#define BITA (0x0400u)
#define BITB (0x0800u)
#define BITC (0x1000u)
#define BITD (0x2000u)
#define BITE (0x4000u)
#define BITF (0x8000u)
#define C (0x0001u)
#define Z (0x0002u)
#define N (0x0004u)
#define V (0x0100u)
#define GIE (0x0008u)
#define CPUOFF (0x0010u)
#define OSCOFF (0x0020u)
#define SCG0 (0x0040u)
#define SCG1 (0x0080u)
#ifndef __IAR_SYSTEMS_ICC__
#define LPM0 (CPUOFF)
#define LPM1 (SCG0+CPUOFF)
#define LPM2 (SCG1+CPUOFF)
#define LPM3 (SCG1+SCG0+CPUOFF)
#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
#else
#define LPM0_bits (CPUOFF)
#define LPM1_bits (SCG0+CPUOFF)
#define LPM2_bits (SCG1+CPUOFF)
#define LPM3_bits (SCG1+SCG0+CPUOFF)
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
#include "in430.h"
#define LPM0 _BIS_SR(LPM0_bits)
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits)
#define LPM1 _BIS_SR(LPM1_bits)
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits)
#define LPM2 _BIS_SR(LPM2_bits)
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits)
#define LPM3 _BIS_SR(LPM3_bits)
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits)
#define LPM4 _BIS_SR(LPM4_bits)
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits)
#endif
#define IE1_ (0x0000u)
DEFC( IE1 , IE1_)
#define WDTIE (0x01)
#define OFIE (0x02)
#define NMIIE (0x10)
#define ACCVIE (0x20)
#define IFG1_ (0x0002u)
DEFC( IFG1 , IFG1_)
#define WDTIFG (0x01)
#define OFIFG (0x02)
#define PORIFG (0x04)
#define RSTIFG (0x08)
#define NMIIFG (0x10)
#define IE2_ (0x0001u)
DEFC( IE2 , IE2_)
#define UC0IE IE2
#define UCA0RXIE (0x01)
#define UCA0TXIE (0x02)
#define UCB0RXIE (0x04)
#define UCB0TXIE (0x08)
#define IFG2_ (0x0003u)
DEFC( IFG2 , IFG2_)
#define UC0IFG IFG2
#define UCA0RXIFG (0x01)
#define UCA0TXIFG (0x02)
#define UCB0RXIFG (0x04)
#define UCB0TXIFG (0x08)
#define __MSP430_HAS_ADC10__
#define ADC10DTC0_ (0x0048u)
DEFC( ADC10DTC0 , ADC10DTC0_)
#define ADC10DTC1_ (0x0049u)
DEFC( ADC10DTC1 , ADC10DTC1_)
#define ADC10AE0_ (0x004Au)
DEFC( ADC10AE0 , ADC10AE0_)
#define ADC10CTL0_ (0x01B0u)
DEFW( ADC10CTL0 , ADC10CTL0_)
#define ADC10CTL1_ (0x01B2u)
DEFW( ADC10CTL1 , ADC10CTL1_)
#define ADC10MEM_ (0x01B4u)
DEFW( ADC10MEM , ADC10MEM_)
#define ADC10SA_ (0x01BCu)
DEFW( ADC10SA , ADC10SA_)
#define ADC10SC (0x001)
#define ENC (0x002)
#define ADC10IFG (0x004)
#define ADC10IE (0x008)
#define ADC10ON (0x010)
#define REFON (0x020)
#define REF2_5V (0x040)
#define MSC (0x080)
#define REFBURST (0x100)
#define REFOUT (0x200)
#define ADC10SR (0x400)
#define ADC10SHT0 (0x800)
#define ADC10SHT1 (0x1000u)
#define SREF0 (0x2000u)
#define SREF1 (0x4000u)
#define SREF2 (0x8000u)
#define ADC10SHT_0 (0*0x800u)
#define ADC10SHT_1 (1*0x800u)
#define ADC10SHT_2 (2*0x800u)
#define ADC10SHT_3 (3*0x800u)
#define SREF_0 (0*0x2000u)
#define SREF_1 (1*0x2000u)
#define SREF_2 (2*0x2000u)
#define SREF_3 (3*0x2000u)
#define SREF_4 (4*0x2000u)
#define SREF_5 (5*0x2000u)
#define SREF_6 (6*0x2000u)
#define SREF_7 (7*0x2000u)
#define ADC10BUSY (0x0001u)
#define CONSEQ0 (0x0002u)
#define CONSEQ1 (0x0004u)
#define ADC10SSEL0 (0x0008u)
#define ADC10SSEL1 (0x0010u)
#define ADC10DIV0 (0x0020u)
#define ADC10DIV1 (0x0040u)
#define ADC10DIV2 (0x0080u)
#define ISSH (0x0100u)
#define ADC10DF (0x0200u)
#define SHS0 (0x0400u)
#define SHS1 (0x0800u)
#define INCH0 (0x1000u)
#define INCH1 (0x2000u)
#define INCH2 (0x4000u)
#define INCH3 (0x8000u)
#define CONSEQ_0 (0*2u)
#define CONSEQ_1 (1*2u)
#define CONSEQ_2 (2*2u)
#define CONSEQ_3 (3*2u)
#define ADC10SSEL_0 (0*8u)
#define ADC10SSEL_1 (1*8u)
#define ADC10SSEL_2 (2*8u)
#define ADC10SSEL_3 (3*8u)
#define ADC10DIV_0 (0*0x20u)
#define ADC10DIV_1 (1*0x20u)
#define ADC10DIV_2 (2*0x20u)
#define ADC10DIV_3 (3*0x20u)
#define ADC10DIV_4 (4*0x20u)
#define ADC10DIV_5 (5*0x20u)
#define ADC10DIV_6 (6*0x20u)
#define ADC10DIV_7 (7*0x20u)
#define SHS_0 (0*0x400u)
#define SHS_1 (1*0x400u)
#define SHS_2 (2*0x400u)
#define SHS_3 (3*0x400u)
#define INCH_0 (0*0x1000u)
#define INCH_1 (1*0x1000u)
#define INCH_2 (2*0x1000u)
#define INCH_3 (3*0x1000u)
#define INCH_4 (4*0x1000u)
#define INCH_5 (5*0x1000u)
#define INCH_6 (6*0x1000u)
#define INCH_7 (7*0x1000u)
#define INCH_8 (8*0x1000u)
#define INCH_9 (9*0x1000u)
#define INCH_10 (10*0x1000u)
#define INCH_11 (11*0x1000u)
#define INCH_12 (12*0x1000u)
#define INCH_13 (13*0x1000u)
#define INCH_14 (14*0x1000u)
#define INCH_15 (15*0x1000u)
#define ADC10FETCH (0x001)
#define ADC10B1 (0x002)
#define ADC10CT (0x004)
#define ADC10TB (0x008)
#define ADC10DISABLE (0x000)
#define __MSP430_HAS_BC2__
#define DCOCTL_ (0x0056u)
DEFC( DCOCTL , DCOCTL_)
#define BCSCTL1_ (0x0057u)
DEFC( BCSCTL1 , BCSCTL1_)
#define BCSCTL2_ (0x0058u)
DEFC( BCSCTL2 , BCSCTL2_)
#define BCSCTL3_ (0x0053u)
DEFC( BCSCTL3 , BCSCTL3_)
#define MOD0 (0x01)
#define MOD1 (0x02)
#define MOD2 (0x04)
#define MOD3 (0x08)
#define MOD4 (0x10)
#define DCO0 (0x20)
#define DCO1 (0x40)
#define DCO2 (0x80)
#define RSEL0 (0x01)
#define RSEL1 (0x02)
#define RSEL2 (0x04)
#define RSEL3 (0x08)
#define DIVA0 (0x10)
#define DIVA1 (0x20)
#define XTS (0x40)
#define XT2OFF (0x80)
#define DIVA_0 (0x00)
#define DIVA_1 (0x10)
#define DIVA_2 (0x20)
#define DIVA_3 (0x30)
#define DIVS0 (0x02)
#define DIVS1 (0x04)
#define SELS (0x08)
#define DIVM0 (0x10)
#define DIVM1 (0x20)
#define SELM0 (0x40)
#define SELM1 (0x80)
#define DIVS_0 (0x00)
#define DIVS_1 (0x02)
#define DIVS_2 (0x04)
#define DIVS_3 (0x06)
#define DIVM_0 (0x00)
#define DIVM_1 (0x10)
#define DIVM_2 (0x20)
#define DIVM_3 (0x30)
#define SELM_0 (0x00)
#define SELM_1 (0x40)
#define SELM_2 (0x80)
#define SELM_3 (0xC0)
#define LFXT1OF (0x01)
#define XT2OF (0x02)
#define XCAP0 (0x04)
#define XCAP1 (0x08)
#define LFXT1S0 (0x10)
#define LFXT1S1 (0x20)
#define XT2S0 (0x40)
#define XT2S1 (0x80)
#define XCAP_0 (0x00)
#define XCAP_1 (0x04)
#define XCAP_2 (0x08)
#define XCAP_3 (0x0C)
#define LFXT1S_0 (0x00)
#define LFXT1S_1 (0x10)
#define LFXT1S_2 (0x20)
#define LFXT1S_3 (0x30)
#define XT2S_0 (0x00)
#define XT2S_1 (0x40)
#define XT2S_2 (0x80)
#define XT2S_3 (0xC0)
#define __MSP430_HAS_CAPLUS__
#define CACTL1_ (0x0059u)
DEFC( CACTL1 , CACTL1_)
#define CACTL2_ (0x005Au)
DEFC( CACTL2 , CACTL2_)
#define CAPD_ (0x005Bu)
DEFC( CAPD , CAPD_)
#define CAIFG (0x01)
#define CAIE (0x02)
#define CAIES (0x04)
#define CAON (0x08)
#define CAREF0 (0x10)
#define CAREF1 (0x20)
#define CARSEL (0x40)
#define CAEX (0x80)
#define CAREF_0 (0x00)
#define CAREF_1 (0x10)
#define CAREF_2 (0x20)
#define CAREF_3 (0x30)
#define CAOUT (0x01)
#define CAF (0x02)
#define P2CA0 (0x04)
#define P2CA1 (0x08)
#define P2CA2 (0x10)
#define P2CA3 (0x20)
#define P2CA4 (0x40)
#define CASHORT (0x80)
#define CAPD0 (0x01)
#define CAPD1 (0x02)
#define CAPD2 (0x04)
#define CAPD3 (0x08)
#define CAPD4 (0x10)
#define CAPD5 (0x20)
#define CAPD6 (0x40)
#define CAPD7 (0x80)
#define __MSP430_HAS_FLASH2__
#define FCTL1_ (0x0128u)
DEFW( FCTL1 , FCTL1_)
#define FCTL2_ (0x012Au)
DEFW( FCTL2 , FCTL2_)
#define FCTL3_ (0x012Cu)
DEFW( FCTL3 , FCTL3_)
#define FRKEY (0x9600u)
#define FWKEY (0xA500u)
#define FXKEY (0x3300u)
#define ERASE (0x0002u)
#define MERAS (0x0004u)
#define WRT (0x0040u)
#define BLKWRT (0x0080u)
#define SEGWRT (0x0080u)
#define FN0 (0x0001u)
#define FN1 (0x0002u)
#ifndef FN2
#define FN2 (0x0004u)
#endif
#ifndef FN3
#define FN3 (0x0008u)
#endif
#ifndef FN4
#define FN4 (0x0010u)
#endif
#define FN5 (0x0020u)
#define FSSEL0 (0x0040u)
#define FSSEL1 (0x0080u)
#define FSSEL_0 (0x0000u)
#define FSSEL_1 (0x0040u)
#define FSSEL_2 (0x0080u)
#define FSSEL_3 (0x00C0u)
#define BUSY (0x0001u)
#define KEYV (0x0002u)
#define ACCVIFG (0x0004u)
#define WAIT (0x0008u)
#define LOCK (0x0010u)
#define EMEX (0x0020u)
#define LOCKA (0x0040u)
#define FAIL (0x0080u)
#define __MSP430_HAS_PORT1_R__
#define __MSP430_HAS_PORT2_R__
#define P1IN_ (0x0020u)
READ_ONLY DEFC( P1IN , P1IN_)
#define P1OUT_ (0x0021u)
DEFC( P1OUT , P1OUT_)
#define P1DIR_ (0x0022u)
DEFC( P1DIR , P1DIR_)
#define P1IFG_ (0x0023u)
DEFC( P1IFG , P1IFG_)
#define P1IES_ (0x0024u)
DEFC( P1IES , P1IES_)
#define P1IE_ (0x0025u)
DEFC( P1IE , P1IE_)
#define P1SEL_ (0x0026u)
DEFC( P1SEL , P1SEL_)
#define P1SEL2_ (0x0041u)
DEFC( P1SEL2 , P1SEL2_)
#define P1REN_ (0x0027u)
DEFC( P1REN , P1REN_)
#define P2IN_ (0x0028u)
READ_ONLY DEFC( P2IN , P2IN_)
#define P2OUT_ (0x0029u)
DEFC( P2OUT , P2OUT_)
#define P2DIR_ (0x002Au)
DEFC( P2DIR , P2DIR_)
#define P2IFG_ (0x002Bu)
DEFC( P2IFG , P2IFG_)
#define P2IES_ (0x002Cu)
DEFC( P2IES , P2IES_)
#define P2IE_ (0x002Du)
DEFC( P2IE , P2IE_)
#define P2SEL_ (0x002Eu)
DEFC( P2SEL , P2SEL_)
#define P2SEL2_ (0x0042u)
DEFC( P2SEL2 , P2SEL2_)
#define P2REN_ (0x002Fu)
DEFC( P2REN , P2REN_)
#define __MSP430_HAS_PORT3_R__
#define P3IN_ (0x0018u)
READ_ONLY DEFC( P3IN , P3IN_)
#define P3OUT_ (0x0019u)
DEFC( P3OUT , P3OUT_)
#define P3DIR_ (0x001Au)
DEFC( P3DIR , P3DIR_)
#define P3SEL_ (0x001Bu)
DEFC( P3SEL , P3SEL_)
#define P3SEL2_ (0x0043u)
DEFC( P3SEL2 , P3SEL2_)
#define P3REN_ (0x0010u)
DEFC( P3REN , P3REN_)
#define __MSP430_HAS_TA3__
#define TA0IV_ (0x012Eu)
READ_ONLY DEFW( TA0IV , TA0IV_)
#define TA0CTL_ (0x0160u)
DEFW( TA0CTL , TA0CTL_)
#define TA0CCTL0_ (0x0162u)
DEFW( TA0CCTL0 , TA0CCTL0_)
#define TA0CCTL1_ (0x0164u)
DEFW( TA0CCTL1 , TA0CCTL1_)
#define TA0CCTL2_ (0x0166u)
DEFW( TA0CCTL2 , TA0CCTL2_)
#define TA0R_ (0x0170u)
DEFW( TA0R , TA0R_)
#define TA0CCR0_ (0x0172u)
DEFW( TA0CCR0 , TA0CCR0_)
#define TA0CCR1_ (0x0174u)
DEFW( TA0CCR1 , TA0CCR1_)
#define TA0CCR2_ (0x0176u)
DEFW( TA0CCR2 , TA0CCR2_)
#define TAIV TA0IV
#define TACTL TA0CTL
#define TACCTL0 TA0CCTL0
#define TACCTL1 TA0CCTL1
#define TACCTL2 TA0CCTL2
#define TAR TA0R
#define TACCR0 TA0CCR0
#define TACCR1 TA0CCR1
#define TACCR2 TA0CCR2
#define TAIV_ TA0IV_
#define TACTL_ TA0CTL_
#define TACCTL0_ TA0CCTL0_
#define TACCTL1_ TA0CCTL1_
#define TACCTL2_ TA0CCTL2_
#define TAR_ TA0R_
#define TACCR0_ TA0CCR0_
#define TACCR1_ TA0CCR1_
#define TACCR2_ TA0CCR2_
#define CCTL0 TACCTL0
#define CCTL1 TACCTL1
#define CCTL2 TACCTL2
#define CCR0 TACCR0
#define CCR1 TACCR1
#define CCR2 TACCR2
#define CCTL0_ TACCTL0_
#define CCTL1_ TACCTL1_
#define CCTL2_ TACCTL2_
#define CCR0_ TACCR0_
#define CCR1_ TACCR1_
#define CCR2_ TACCR2_
#define TASSEL1 (0x0200u)
#define TASSEL0 (0x0100u)
#define ID1 (0x0080u)
#define ID0 (0x0040u)
#define MC1 (0x0020u)
#define MC0 (0x0010u)
#define TACLR (0x0004u)
#define TAIE (0x0002u)
#define TAIFG (0x0001u)
#define MC_0 (0*0x10u)
#define MC_1 (1*0x10u)
#define MC_2 (2*0x10u)
#define MC_3 (3*0x10u)
#define ID_0 (0*0x40u)
#define ID_1 (1*0x40u)
#define ID_2 (2*0x40u)
#define ID_3 (3*0x40u)
#define TASSEL_0 (0*0x100u)
#define TASSEL_1 (1*0x100u)
#define TASSEL_2 (2*0x100u)
#define TASSEL_3 (3*0x100u)
#define CM1 (0x8000u)
#define CM0 (0x4000u)
#define CCIS1 (0x2000u)
#define CCIS0 (0x1000u)
#define SCS (0x0800u)
#define SCCI (0x0400u)
#define CAP (0x0100u)
#define OUTMOD2 (0x0080u)
#define OUTMOD1 (0x0040u)
#define OUTMOD0 (0x0020u)
#define CCIE (0x0010u)
#define CCI (0x0008u)
#define OUT (0x0004u)
#define COV (0x0002u)
#define CCIFG (0x0001u)
#define OUTMOD_0 (0*0x20u)
#define OUTMOD_1 (1*0x20u)
#define OUTMOD_2 (2*0x20u)
#define OUTMOD_3 (3*0x20u)
#define OUTMOD_4 (4*0x20u)
#define OUTMOD_5 (5*0x20u)
#define OUTMOD_6 (6*0x20u)
#define OUTMOD_7 (7*0x20u)
#define CCIS_0 (0*0x1000u)
#define CCIS_1 (1*0x1000u)
#define CCIS_2 (2*0x1000u)
#define CCIS_3 (3*0x1000u)
#define CM_0 (0*0x4000u)
#define CM_1 (1*0x4000u)
#define CM_2 (2*0x4000u)
#define CM_3 (3*0x4000u)
#define TA0IV_NONE (0x0000u)
#define TA0IV_TACCR1 (0x0002u)
#define TA0IV_TACCR2 (0x0004u)
#define TA0IV_6 (0x0006u)
#define TA0IV_8 (0x0008u)
#define TA0IV_TAIFG (0x000Au)
#define __MSP430_HAS_T1A3__
#define TA1IV_ (0x011Eu)
READ_ONLY DEFW( TA1IV , TA1IV_)
#define TA1CTL_ (0x0180u)
DEFW( TA1CTL , TA1CTL_)
#define TA1CCTL0_ (0x0182u)
DEFW( TA1CCTL0 , TA1CCTL0_)
#define TA1CCTL1_ (0x0184u)
DEFW( TA1CCTL1 , TA1CCTL1_)
#define TA1CCTL2_ (0x0186u)
DEFW( TA1CCTL2 , TA1CCTL2_)
#define TA1R_ (0x0190u)
DEFW( TA1R , TA1R_)
#define TA1CCR0_ (0x0192u)
DEFW( TA1CCR0 , TA1CCR0_)
#define TA1CCR1_ (0x0194u)
DEFW( TA1CCR1 , TA1CCR1_)
#define TA1CCR2_ (0x0196u)
DEFW( TA1CCR2 , TA1CCR2_)
#define TA1IV_NONE (0x0000u)
#define TA1IV_TACCR1 (0x0002u)
#define TA1IV_TACCR2 (0x0004u)
#define TA1IV_TAIFG (0x000Au)
#define __MSP430_HAS_USCI__
#define UCA0CTL0_ (0x0060u)
DEFC( UCA0CTL0 , UCA0CTL0_)
#define UCA0CTL1_ (0x0061u)
DEFC( UCA0CTL1 , UCA0CTL1_)
#define UCA0BR0_ (0x0062u)
DEFC( UCA0BR0 , UCA0BR0_)
#define UCA0BR1_ (0x0063u)
DEFC( UCA0BR1 , UCA0BR1_)
#define UCA0MCTL_ (0x0064u)
DEFC( UCA0MCTL , UCA0MCTL_)
#define UCA0STAT_ (0x0065u)
DEFC( UCA0STAT , UCA0STAT_)
#define UCA0RXBUF_ (0x0066u)
READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_)
#define UCA0TXBUF_ (0x0067u)
DEFC( UCA0TXBUF , UCA0TXBUF_)
#define UCA0ABCTL_ (0x005Du)
DEFC( UCA0ABCTL , UCA0ABCTL_)
#define UCA0IRTCTL_ (0x005Eu)
DEFC( UCA0IRTCTL , UCA0IRTCTL_)
#define UCA0IRRCTL_ (0x005Fu)
DEFC( UCA0IRRCTL , UCA0IRRCTL_)
#define UCB0CTL0_ (0x0068u)
DEFC( UCB0CTL0 , UCB0CTL0_)
#define UCB0CTL1_ (0x0069u)
DEFC( UCB0CTL1 , UCB0CTL1_)
#define UCB0BR0_ (0x006Au)
DEFC( UCB0BR0 , UCB0BR0_)
#define UCB0BR1_ (0x006Bu)
DEFC( UCB0BR1 , UCB0BR1_)
#define UCB0I2CIE_ (0x006Cu)
DEFC( UCB0I2CIE , UCB0I2CIE_)
#define UCB0STAT_ (0x006Du)
DEFC( UCB0STAT , UCB0STAT_)
#define UCB0RXBUF_ (0x006Eu)
READ_ONLY DEFC( UCB0RXBUF , UCB0RXBUF_)
#define UCB0TXBUF_ (0x006Fu)
DEFC( UCB0TXBUF , UCB0TXBUF_)
#define UCB0I2COA_ (0x0118u)
DEFW( UCB0I2COA , UCB0I2COA_)
#define UCB0I2CSA_ (0x011Au)
DEFW( UCB0I2CSA , UCB0I2CSA_)
// UART-Mode Bits
#define UCPEN (0x80)
#define UCPAR (0x40)
#define UCMSB (0x20)
#define UC7BIT (0x10)
#define UCSPB (0x08)
#define UCMODE1 (0x04)
#define UCMODE0 (0x02)
#define UCSYNC (0x01)
// SPI-Mode Bits
#define UCCKPH (0x80)
#define UCCKPL (0x40)
#define UCMST (0x08)
// I2C-Mode Bits
#define UCA10 (0x80)
#define UCSLA10 (0x40)
#define UCMM (0x20)
//#define res (0x10)
#define UCMODE_0 (0x00)
#define UCMODE_1 (0x02)
#define UCMODE_2 (0x04)
#define UCMODE_3 (0x06)
// UART-Mode Bits
#define UCSSEL1 (0x80)
#define UCSSEL0 (0x40)
#define UCRXEIE (0x20)
#define UCBRKIE (0x10)
#define UCDORM (0x08)
#define UCTXADDR (0x04)
#define UCTXBRK (0x02)
#define UCSWRST (0x01)
// SPI-Mode Bits
//#define res (0x20)
//#define res (0x10)
//#define res (0x08)
//#define res (0x04)
//#define res (0x02)
// I2C-Mode Bits
//#define res (0x20)
#define UCTR (0x10)
#define UCTXNACK (0x08)
#define UCTXSTP (0x04)
#define UCTXSTT (0x02)
#define UCSSEL_0 (0x00)
#define UCSSEL_1 (0x40)
#define UCSSEL_2 (0x80)
#define UCSSEL_3 (0xC0)
#define UCBRF3 (0x80)
#define UCBRF2 (0x40)
#define UCBRF1 (0x20)
#define UCBRF0 (0x10)
#define UCBRS2 (0x08)
#define UCBRS1 (0x04)
#define UCBRS0 (0x02)
#define UCOS16 (0x01)
#define UCBRF_0 (0x00)
#define UCBRF_1 (0x10)
#define UCBRF_2 (0x20)
#define UCBRF_3 (0x30)
#define UCBRF_4 (0x40)
#define UCBRF_5 (0x50)
#define UCBRF_6 (0x60)
#define UCBRF_7 (0x70)
#define UCBRF_8 (0x80)
#define UCBRF_9 (0x90)
#define UCBRF_10 (0xA0)
#define UCBRF_11 (0xB0)
#define UCBRF_12 (0xC0)
#define UCBRF_13 (0xD0)
#define UCBRF_14 (0xE0)
#define UCBRF_15 (0xF0)
#define UCBRS_0 (0x00)
#define UCBRS_1 (0x02)
#define UCBRS_2 (0x04)
#define UCBRS_3 (0x06)
#define UCBRS_4 (0x08)
#define UCBRS_5 (0x0A)
#define UCBRS_6 (0x0C)
#define UCBRS_7 (0x0E)
#define UCLISTEN (0x80)
#define UCFE (0x40)
#define UCOE (0x20)
#define UCPE (0x10)
#define UCBRK (0x08)
#define UCRXERR (0x04)
#define UCADDR (0x02)
#define UCBUSY (0x01)
#define UCIDLE (0x02)
//#define res (0x80)
//#define res (0x40)
//#define res (0x20)
//#define res (0x10)
#define UCNACKIE (0x08)
#define UCSTPIE (0x04)
#define UCSTTIE (0x02)
#define UCALIE (0x01)
#define UCSCLLOW (0x40)
#define UCGC (0x20)
#define UCBBUSY (0x10)
#define UCNACKIFG (0x08)
#define UCSTPIFG (0x04)
#define UCSTTIFG (0x02)
#define UCALIFG (0x01)
#define UCIRTXPL5 (0x80)
#define UCIRTXPL4 (0x40)
#define UCIRTXPL3 (0x20)
#define UCIRTXPL2 (0x10)
#define UCIRTXPL1 (0x08)
#define UCIRTXPL0 (0x04)
#define UCIRTXCLK (0x02)
#define UCIREN (0x01)
#define UCIRRXFL5 (0x80)
#define UCIRRXFL4 (0x40)
#define UCIRRXFL3 (0x20)
#define UCIRRXFL2 (0x10)
#define UCIRRXFL1 (0x08)
#define UCIRRXFL0 (0x04)
#define UCIRRXPL (0x02)
#define UCIRRXFE (0x01)
//#define res (0x80)
//#define res (0x40)
#define UCDELIM1 (0x20)
#define UCDELIM0 (0x10)
#define UCSTOE (0x08)
#define UCBTOE (0x04)
//#define res (0x02)
#define UCABDEN (0x01)
#define UCGCEN (0x8000u)
#define UCOA9 (0x0200u)
#define UCOA8 (0x0100u)
#define UCOA7 (0x0080u)
#define UCOA6 (0x0040u)
#define UCOA5 (0x0020u)
#define UCOA4 (0x0010u)
#define UCOA3 (0x0008u)
#define UCOA2 (0x0004u)
#define UCOA1 (0x0002u)
#define UCOA0 (0x0001u)
#define UCSA9 (0x0200u)
#define UCSA8 (0x0100u)
#define UCSA7 (0x0080u)
#define UCSA6 (0x0040u)
#define UCSA5 (0x0020u)
#define UCSA4 (0x0010u)
#define UCSA3 (0x0008u)
#define UCSA2 (0x0004u)
#define UCSA1 (0x0002u)
#define UCSA0 (0x0001u)
#define __MSP430_HAS_WDT__
#define WDTCTL_ (0x0120u)
DEFW( WDTCTL , WDTCTL_)
#define WDTIS0 (0x0001u)
#define WDTIS1 (0x0002u)
#define WDTSSEL (0x0004u)
#define WDTCNTCL (0x0008u)
#define WDTTMSEL (0x0010u)
#define WDTNMI (0x0020u)
#define WDTNMIES (0x0040u)
#define WDTHOLD (0x0080u)
#define WDTPW (0x5A00u)
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL)
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)
#define WDT_MRST_32 (WDTPW+WDTCNTCL)
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0)
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1)
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0)
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL)
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0)
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1)
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)
#ifndef __DisableCalData
#define CALDCO_16MHZ_ (0x10F8u)
READ_ONLY DEFC( CALDCO_16MHZ , CALDCO_16MHZ_)
#define CALBC1_16MHZ_ (0x10F9u)
READ_ONLY DEFC( CALBC1_16MHZ , CALBC1_16MHZ_)
#define CALDCO_12MHZ_ (0x10FAu)
READ_ONLY DEFC( CALDCO_12MHZ , CALDCO_12MHZ_)
#define CALBC1_12MHZ_ (0x10FBu)
READ_ONLY DEFC( CALBC1_12MHZ , CALBC1_12MHZ_)
#define CALDCO_8MHZ_ (0x10FCu)
READ_ONLY DEFC( CALDCO_8MHZ , CALDCO_8MHZ_)
#define CALBC1_8MHZ_ (0x10FDu)
READ_ONLY DEFC( CALBC1_8MHZ , CALBC1_8MHZ_)
#define CALDCO_1MHZ_ (0x10FEu)
READ_ONLY DEFC( CALDCO_1MHZ , CALDCO_1MHZ_)
#define CALBC1_1MHZ_ (0x10FFu)
READ_ONLY DEFC( CALBC1_1MHZ , CALBC1_1MHZ_)
#endif
#define PORT1_VECTOR (2 * 2u)
#define PORT2_VECTOR (3 * 2u)
#define ADC10_VECTOR (5 * 2u)
#define USCIAB0TX_VECTOR (6 * 2u)
#define USCIAB0RX_VECTOR (7 * 2u)
#define TIMER0_A1_VECTOR (8 * 2u)
#define TIMER0_A0_VECTOR (9 * 2u)
#define WDT_VECTOR (10 * 2u)
#define COMPARATORA_VECTOR (11 * 2u)
#define TIMER1_A1_VECTOR (12 * 2u)
#define TIMER1_A0_VECTOR (13 * 2u)
#define NMI_VECTOR (14 * 2u)
#define RESET_VECTOR (15 * 2u)
#pragma language=default
#endif
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