//Enable/Start sampling and conversion
/*
* Base address of ADC12B Module
* Start the conversion into memory buffer 0
* Use the single-channel, single-conversion mode
*/
ADC12_B_startConversion(ADC12_B_BASE,
ADC12_B_MEMORY_0,
ADC12_B_SEQOFCHANNELS);
// __bis_SR_register(LPM3_bits | GIE); // Wait for conversion to complete
// __bic_SR_register(GIE);
}
3.AD中断
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC12_VECTOR
__interrupt
#elif defined(__GNUC__)
__attribute__((interrupt(ADC12_VECTOR)))
#endif
void ADC12_ISR(void)
{
switch(__even_in_range(ADC12IV,12))
{
case 0: break; // Vector 0: No interrupt
case 2: break; // Vector 2: ADC12BMEMx Overflow
case 4: break; // Vector 4: Conversion time overflow
case 6: break; // Vector 6: ADC12BHI
case 8: break; // Vector 8: ADC12BLO
case 10: break; // Vector 10: ADC12BIN
case 12:
// Vector 12: ADC12BMEM0 Interrupt
ADC12IFGR0 &= ~ADC12IFG0; // Clear interrupt flag
__bic_SR_register_on_exit(LPM3_bits); // Exit active CPU
break; // Clear CPUOFF bit from 0(SR)
case 14:
ADC12IFGR0 &= ~ADC12IFG1; // Clear interrupt flag
__bic_SR_register_on_exit(LPM3_bits); // Exit active CPU
break; // Vector 14: ADC12BMEM1
case 16:
ADC12IFGR0 &= ~ADC12IFG2; // Clear interrupt flag
__bic_SR_register_on_exit(LPM3_bits); // Exit active CPU
break; // Vector 16: ADC12BMEM2
case 18:
qInput[samp_count] = ADC12_B_getResults(ADC12_B_BASE, ADC12_B_MEMORY_0);
samp_count++;
if(samp_count >=256)
{
samp_count =0;
mode = 1;
__bic_SR_register_on_exit(LPM3_bits); // Exit active CPU
// Disable ADC12 and Timer_A0
ADC12_B_disable(ADC12_B_BASE);
Timer_B_stop(TIMER_B0_BASE);
}
__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU //退出LPM0
break; // Vector 18: ADC12BMEM3
case 20: break; // Vector 20: ADC12BMEM4
case 22: break; // Vector 22: ADC12BMEM5
case 24: break; // Vector 24: ADC12BMEM6
case 26: break; // Vector 26: ADC12BMEM7
case 28: break; // Vector 28: ADC12BMEM8
case 30: break; // Vector 30: ADC12BMEM9
case 32: break; // Vector 32: ADC12BMEM10
case 34: break; // Vector 34: ADC12BMEM11
case 36: break; // Vector 36: ADC12BMEM12
case 38: break; // Vector 38: ADC12BMEM13
case 40: break; // Vector 40: ADC12BMEM14
case 42: break; // Vector 42: ADC12BMEM15
case 44: break; // Vector 44: ADC12BMEM16
case 46: break; // Vector 46: ADC12BMEM17
case 48: break; // Vector 48: ADC12BMEM18
case 50: break; // Vector 50: ADC12BMEM19
case 52: break; // Vector 52: ADC12BMEM20
case 54: break; // Vector 54: ADC12BMEM21
case 56: break; // Vector 56: ADC12BMEM22
case 58: break; // Vector 58: ADC12BMEM23
case 60: break; // Vector 60: ADC12BMEM24
case 62: break; // Vector 62: ADC12BMEM25
case 64: break; // Vector 64: ADC12BMEM26
case 66: break; // Vector 66: ADC12BMEM27
case 68: break; // Vector 68: ADC12BMEM28
case 70: break; // Vector 70: ADC12BMEM29
case 72: break; // Vector 72: ADC12BMEM30
case 74: break; // Vector 74: ADC12BMEM31
case 76: break; // Vector 76: ADC12BRDY
default: break;
}
}