|
我的设置跟楼上的一样的 下面是output信息
Mon Mar 21, 2016 14:40:25: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\TexasInstruments\MSP432P401R.dmac
Mon Mar 21, 2016 14:40:25: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\TexasInstruments\FlashMSP432P4.mac
Mon Mar 21, 2016 14:40:26: Logging to file: D:\WorkingDir\Msp432\ucos_3rd\Micrium\Examples\TI\MSP-EXP432P401R\OS3\IAR\cspycomm.log
Mon Mar 21, 2016 14:40:26: JLINK command: ProjectFile = D:\WorkingDir\Msp432\ucos_3rd\Micrium\Examples\TI\MSP-EXP432P401R\OS3\IAR\settings\OS3_Debug.jlink, return = 0
Mon Mar 21, 2016 14:40:26: JLINK command: scriptfile = C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\TexasInstruments\MSP432P4xx.JLinkScript, return = 0
Mon Mar 21, 2016 14:40:26: Device "MSP432P401R" selected.
Mon Mar 21, 2016 14:40:26: DLL version: V5.2c, compiled Sep 10 2015 17:39:31
Mon Mar 21, 2016 14:40:26: Firmware: J-Link V9 compiled Sep 18 2015 19:53:12
Mon Mar 21, 2016 14:40:26: Selecting SWD as current target interface.
Mon Mar 21, 2016 14:40:26: JTAG speed is initially set to: 12000 kHz
Mon Mar 21, 2016 14:40:26: ******************************
Mon Mar 21, 2016 14:40:26: * J-Link script: MSP432P401R *
Mon Mar 21, 2016 14:40:26: ******************************
Mon Mar 21, 2016 14:40:26: CPUID register: 0xFFFFFFFF
Mon Mar 21, 2016 14:40:36: Found SWD-DP with ID 0x2BA01477
Mon Mar 21, 2016 14:40:36: SWD speed too high. Reduced from 12000 kHz to 3416 kHz for stability
Mon Mar 21, 2016 14:40:36: Found Cortex-M4 r0p1, Little endian.
Mon Mar 21, 2016 14:40:36: FPUnit: 6 code (BP) slots and 2 literal slots
Mon Mar 21, 2016 14:40:36: CoreSight components:
Mon Mar 21, 2016 14:40:36: ROMTbl 0 @ E00FF000
Mon Mar 21, 2016 14:40:36: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Mon Mar 21, 2016 14:40:36: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Mon Mar 21, 2016 14:40:36: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Mon Mar 21, 2016 14:40:36: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Mon Mar 21, 2016 14:40:36: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Mon Mar 21, 2016 14:40:36: Hardware reset with strategy 1 was performed
Mon Mar 21, 2016 14:40:36: Initial reset was performed
Mon Mar 21, 2016 14:40:36: Resetting device to restore clock configuration
Mon Mar 21, 2016 14:40:36: Hardware reset with strategy 1 was performed
Mon Mar 21, 2016 14:40:36: Halting watchdog timer
Mon Mar 21, 2016 14:40:36: Clearing PCM_CTL LOCK_SD and LOCK_RTC bits
Mon Mar 21, 2016 14:40:36: Enabling all SRAM banks
Mon Mar 21, 2016 14:40:36: 2560 bytes downloaded and verified (16.03 Kbytes/sec)
Mon Mar 21, 2016 14:40:36: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\TexasInstruments\FlashMSP432P4.out
Mon Mar 21, 2016 14:40:36: Target reset
Mon Mar 21, 2016 14:40:49: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\TexasInstruments\FlashMSP432P4.mac
|
|