Modelsim 仿真后总是no extended dataflow license exists@【FPGA/CPLD】

feikufeirong

Modelsim 仿真后总是no extended dataflow license exists@【FPGA/CPLD】 [复制链接]

code反复检查了应该没有问题 compile之后 同时simulate counter.vhd 和 counter.tb.vhd后不弹出波形页面，这时候再打开simulate 就只剩counter.vhd了
看了一些帖子，说出现no extended dataflow license exists 是signal matching有问题，但这么简单的一个小程序不应该啊

feikufeirong

这是tb的
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;


ENTITY count_0_to_5_tb IS
END count_0_to_5_tb;

ARCHITECTURE behavior OF count_0_to_5_tb IS
   
    COMPONENT count_0_to_5  
    PORT(clk : IN  std_logic;
         count : buffer  std_logic_vector(2 downto 0);
         reset_n : IN  std_logic;
                        Q: out std_logic
        );
    END COMPONENT;

   signal clk : std_logic := '0';
   signal reset_n : std_logic := '1';

   signal count : std_logic_vector(2 downto 0);
        signal Q: std_logic;
   
   constant clk_period : time := 1 ms;
BEGIN
   
   uut: count_0_to_5 PORT MAP (
          clk => clk,
          count => count,
          reset_n => reset_n,
                         Q => Q
        );      

   
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
  
  stim_proc: process
   begin         
        wait for 1 ms;
        reset_n <='0';
        wait for 1 ms;
        reset_n <='1';
        
  end process;

END;

feikufeirong

这是0-5 counter，Q用来表示有没有数到5
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity count_0_to_5 is
port (clk : in std_logic;
      count : buffer std_logic_vector(2 downto 0);
      reset_n :in std_logic;
                Q: out std_logic
      );
end count_0_to_5;

architecture Behavior of count_0_to_5 is


begin


process(clk,reset_n)
begin
  
  if(rising_edge(clk)) then
    if (count="101")then
            count<=(others=>'0');

         else count<=count + '1';

         end if;
  end if;
  
  if (count="101") then
     Q<='1';
  else Q<='0';
  end if;
  
  if(reset_n='1') then
     count<=(others=>'0');
  end if;
end process;






end Behavior;

zhangdaijinqf

feikufeirong

晤。。。真的没人吗

coyoo

要先看文件编译能否通过