#define PRD 25000/2
#define PI 3.1415926
// Global variables
Uint16 dataC; // Received data for SCI-A
//Uint16 dataB; // Rceived data for SCI-A
Uint16 N=60;
Uint16 g;
float M=0.8;
int i=0;
void main(void)
{
Uint16 ReceivedChar;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
InitGpio();
// Setup only the GP I/O only for SCI-A and SCI-B functionality
// This function is found in DSP2833x_Sci.c
InitSciGpio();
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
EALLOW;
PieVectTable.EPWM1_INT = &epwm1_isr;
// PieVectTable.ADCINT=&adc_isr;
EDIS;
#if UART_INT
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
#if SCI
PieVectTable.SCIRXINTB = &scibRxFifoIsr;
PieVectTable.SCITXINTB = &scibTxFifoIsr;
#else
PieVectTable.SCIRXINTC = &scicRxFifoIsr;
PieVectTable.SCITXINTC = &scicTxFifoIsr;
#endif
EDIS; // This is needed to disable write to EALLOW protected registers
#endif
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// Step 5. User specific code, enable interrupts:
#if UART_INT
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
#if SCI
PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 RE
PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 TX
IFR = 0x0000;
IER = 0x100; // Enable CPU INT
#else
PieCtrlRegs.PIEIER8.bit.INTx5=1; // PIE Group 8, int5 RE
PieCtrlRegs.PIEIER8.bit.INTx6=1; // PIE Group 8, INT6 TX
IFR = 0x0000;
IER = 0x080; // Enable CPU INT
#endif
EINT;
#endif
// Step 6. IDLE loop. Just sit and loop forever (optional):
while(1)
{
#if UART_INT==0
#if SCI
while(ScibRegs.SCIFFRX.bit.RXFFST == 0); { } // wait for RRDY/RXFFST =1 for 1 data available in FIFO
ReceivedChar = ScibRegs.SCIRXBUF.all;
// ScibRegs.SCITXBUF=dataB;
// f=dataB;
N=3000/ReceivedChar;
M=0.8*ReceivedChar/50;
// while(ScibRegs.SCIFFTX.bit.TXFFST != 0);
scib_xmit(ReceivedChar);
if(ReceivedChar==0xc1)
{pwm();}
#else
while(ScicRegs.SCIFFRX.bit.RXFFST == 0); { } // wait for RRDY/RXFFST =1 for 1 data available in FIFO
dataC = ScicRegs.SCIRXBUF.all;
ScicRegs.SCITXBUF= dataC;
while(ScicRegs.SCIFFTX.bit.TXFFST != 0);
#endif
#else
for(;;);
#endif
}
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL= 1; // Select SOC from CTR=0
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
}
void InitEPwm2()
{
EPwm2Regs.TBPRD = PRD; // Period = 1600 TBCLK counts
EPwm2Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through？？？
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBFED = 50; // FED = 50 TBCLKs
EPwm2Regs.DBRED = 50; // RED = 50 TBCLKs
EPwm2Regs.ETSEL.bit.INTEN=0;
// EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
// EPwm2Regs.ETSEL.bit.SOCASEL = 2; // Select SOC from from CPMA on upcount
// EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event ？？
}
void InitEPwm3()
{
EPwm3Regs.TBPRD = PRD; // Period = 1600 TBCLK counts
EPwm3Regs.TBPHS.half.TBPHSHR = 0; // Set Phase register to zero
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM3A
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
PieCtrlRegs.PIEACK.all=PIEACK_GROUP3;
}
/*interrupt void scibTxFifoIsr(void)
{
ScibRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}
interrupt void scibRxFifoIsr(void)
{
dataB=ScibRegs.SCIRXBUF.all; // Read data
ScibRegs.SCITXBUF=dataB; // Send data
ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
ScibRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack
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