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本帖最后由 ltbytyn 于 2014-11-30 23:50 编辑
在“【TI首届低功耗设计大赛】三轴加速度演示”中MSP430FR5969使用 IO模拟I2C驱动ADXL345三轴加速度芯片(使用IO模拟I2C的原因也在上文中说过)。事实上,MSP430FR5969本身有硬件的I2C模块。使用硬件I2C(eUSCI除了可配置为UART模式,还可配置为I2C模式工作,当然也可配置为SPI模式),不论效率、稳定性都是IO模拟无法比较的。I2c模块参数
I2C硬件框图
拓扑结构
数据发送
MSP430FR5969中硬件I2C模块支持7位和10位2种地址模式。
7位地址模式
10位地址模式
- #include "driverlib.h"
- //******************************************************************************
- // Demo - EUSCI_B0 I2C Master TX bytes to Multiple Slaves
- //
- // Description: This demo connects two MSP430's via the I2C bus.
- // The master transmits to 4 different I2C slave addresses 0x0A,0x0B,0x0C&0x0D.
- // Each slave address has a specific related data in the array TXData[].
- // At the end of four I2C transactions the slave address rolls over and begins
- // again at 0x0A.
- // ACLK = n/a, MCLK = SMCLK = BRCLK = default DCO = ~1.045MHz
- //
- // /|\ /|\
- // MSP430FR5969 10k 10k MSP430FR5969
- // slave | | master
- // ----------------- | | -----------------
- // -|XIN P1.6/UCB0SDA|<-|----+->|P1.6/UCB0SDA XIN|-
- // | | | | |
- // -|XOUT | | | XOUT|-
- // | P1.7/UCB0SCL|<-+------>|P1.7/UCB0SCL |
- // | | | |
- //
- //******************************************************************************
- uint8_t TXData[] = { 0xA1, 0xB1, 0xC1, 0xD1 }; // Pointer to TX data
- uint8_t SlaveAddress[] = { 0x0A, 0x0B, 0x0C, 0x0D };
- uint8_t TXByteCtr;
- uint8_t SlaveFlag = 0;
- void main(void)
- {
- WDT_A_hold(WDT_A_BASE);
- //Set DCO frequency to 1MHz
- CS_setDCOFreq(CS_DCORSEL_0, CS_DCOFSEL_0);
- //Set ACLK = VLO with frequency divider of 1
- CS_clockSignalInit(CS_ACLK, CS_VLOCLK_SELECT, CS_CLOCK_DIVIDER_1);
- //Set SMCLK = DCO with frequency divider of 1
- CS_clockSignalInit(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
- //Set MCLK = DCO with frequency divider of 1
- CS_clockSignalInit(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
- // Configure Pins for I2C
- //Set P1.6 and P1.7 as Secondary Module Function Input.
- /*
- * Select Port 1
- * Set Pin 6, 7 to input Secondary Module Function, (UCB0SIMO/UCB0SDA, UCB0SOMI/UCB0SCL).
- */
- GPIO_setAsPeripheralModuleFunctionInputPin(
- GPIO_PORT_P1,
- GPIO_PIN6 + GPIO_PIN7,
- GPIO_SECONDARY_MODULE_FUNCTION
- );
- /*
- * Disable the GPIO power-on default high-impedance mode to activate
- * previously configured port settings
- */
- PMM_unlockLPM5();
- EUSCI_B_I2C_masterInit(EUSCI_B0_BASE,
- EUSCI_B_I2C_CLOCKSOURCE_SMCLK,
- CS_getSMCLK(),
- EUSCI_B_I2C_SET_DATA_RATE_400KBPS,
- 0,
- EUSCI_B_I2C_NO_AUTO_STOP
- );
- //Set Master in receive mode
- EUSCI_B_I2C_setMode(EUSCI_B0_BASE,
- EUSCI_B_I2C_TRANSMIT_MODE
- );
- //Enable I2C Module to start operations
- EUSCI_B_I2C_enable(EUSCI_B0_BASE);
- EUSCI_B_I2C_clearInterruptFlag(EUSCI_B0_BASE,
- EUSCI_B_I2C_TRANSMIT_INTERRUPT0 +
- EUSCI_B_I2C_NAK_INTERRUPT
- );
- //Enable master Receive interrupt
- EUSCI_B_I2C_enableInterrupt(EUSCI_B0_BASE,
- EUSCI_B_I2C_TRANSMIT_INTERRUPT0 +
- EUSCI_B_I2C_NAK_INTERRUPT
- );
- SlaveFlag = 0;
- while (1) {
- //Specify slave address
- EUSCI_B_I2C_setSlaveAddress(EUSCI_B0_BASE,
- SlaveAddress[SlaveFlag]
- );
- TXByteCtr = 1; // Load TX byte counter
- while (EUSCI_B_I2C_SENDING_STOP == EUSCI_B_I2C_masterIsSTOPSent
- (EUSCI_B0_BASE)) ;
- EUSCI_B_I2C_masterSendStart(EUSCI_B0_BASE);
- __bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
- // Remain in LPM0 until all data
- // is TX'd
- // Change Slave address
- SlaveFlag++;
- if (SlaveFlag > 3) { // Roll over slave address
- SlaveFlag = 0;
- __delay_cycles(1000); // Delay between transmissions
- }
- }
- }
- #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
- #pragma vector=USCI_B0_VECTOR
- __interrupt
- #elif defined(__GNUC__)
- __attribute__((interrupt(USCI_B0_VECTOR)))
- #endif
- void USCIB0_ISR(void)
- {
- switch (__even_in_range(UCB0IV, 0x1E)) {
- case 0x00: break; // Vector 0: No interrupts break;
- case 0x02: break;
- case 0x04:
- EUSCI_B_I2C_masterSendStart(EUSCI_B0_BASE);
- break; // Vector 4: NACKIFG break;
- case 0x06: break; // Vector 6: STTIFG break;
- case 0x08: break; // Vector 8: STPIFG break;
- case 0x0a: break; // Vector 10: RXIFG3 break;
- case 0x0c: break; // Vector 14: TXIFG3 break;
- case 0x0e: break; // Vector 16: RXIFG2 break;
- case 0x10: break; // Vector 18: TXIFG2 break;
- case 0x12: break; // Vector 20: RXIFG1 break;
- case 0x14: break; // Vector 22: TXIFG1 break;
- case 0x16: break; // Vector 24: RXIFG0 break;
- case 0x18:
- if (TXByteCtr) { // Check TX byte counter
- EUSCI_B_I2C_masterMultiByteSendNext(EUSCI_B0_BASE,
- TXData[SlaveFlag]);
- TXByteCtr--; // Decrement TX byte counter
- }else {
- EUSCI_B_I2C_masterMultiByteSendStop(EUSCI_B0_BASE);
- __bic_SR_register_on_exit(CPUOFF); // Exit LPM0
- }
- break; // Vector 26: TXIFG0 break;
- default: break;
- }
- }
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