library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RS232 IS
PORT (
clock : IN std_logic;
txd : OUT std_logic);
END RS232;
ARCHITECTURE arch OF RS232 IS
SIGNAL txd_reg : std_logic;
SIGNAL count : std_logic_vector(11 DOWNTO 0);
SIGNAL bitcnt_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL bit_start : std_logic;
SIGNAL uart_buf : std_logic_vector(7 DOWNTO 0);
SIGNAL txd_xhdl1 : std_logic;
BEGIN
txd <= txd_xhdl1;
PROCESS
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
IF (count < "101000101100") THEN
count <= count + "000000000001";
bit_start <= '0';
ELSE
count <= "000000000000";
bit_start <= '1';
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (bit_start'EVENT AND bit_start = '1');
uart_buf <= "11111111";
IF (bitcnt_reg < "1001") THEN
bitcnt_reg <= bitcnt_reg + "0001";
ELSE
bitcnt_reg <= "0000";
END IF;
IF (uart_buf /= "01001001") THEN
CASE bitcnt_reg IS
WHEN "0000" =>
txd_reg <= '0';
WHEN "0001" =>
txd_reg <= uart_buf(0);
WHEN "0010" =>
txd_reg <= uart_buf(1);
WHEN "0011" =>
txd_reg <= uart_buf(2);
WHEN "0100" =>
txd_reg <= uart_buf(3);
WHEN "0101" =>
txd_reg <= uart_buf(4);
WHEN "0110" =>
txd_reg <= uart_buf(5);
WHEN "0111" =>
txd_reg <= uart_buf(6);
WHEN "1000" =>
txd_reg <= uart_buf(7);
WHEN "1001" =>
txd_reg <= '1';
WHEN OTHERS =>
txd_reg <= '1';
END CASE;
END IF;
END PROCESS;
txd_xhdl1 <= txd_reg ;