JD642CPLD逻辑代码

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JD642CPLD逻辑代码 [复制链接]

// LOGIC: EPM3064 AutoFocus System glue logic // MODULE NAME: JD642 // FILE NAME: JD642.v // COMPANY: TINY NEST // DESIGNER: ZJD // REVISION HISTORY: 1.0 // Revision 1.0 9/12/2007 // Description: glue-logic for JD642 module JD642 (CENS,EAH,FLASHA_H,GPIOH,LEDS, EA6,SDWEN,SDCASN,SDRASN,TDOEN,CSFLASHN,CSSAN,CSSBN,EREN,EWEN, RST_SYSN,WDI,PFON,REST_DSPN,REST,RESTN,INTA,INTB,GPIO4,GPIO5,GPIO6,GPIO7, CLK50M,CLK25LXT,CLK25PLL,FLASHWPN,ALM_Q,ALM_S,RESV,RT485); input [3:0] CENS; input [22:19] EAH; input [12:9] GPIOH; input EA6,SDWEN,SDCASN,SDRASN,RST_SYSN,PFON,INTA,INTB,CLK50M,GPIO6,GPIO7; output [22:19] FLASHA_H; output [1:0] LEDS; output TDOEN,CSFLASHN,CSSAN,CSSBN,EREN,EWEN,WDI,REST_DSPN,REST,RESTN,GPIO4,GPIO5, CLK25LXT,CLK25PLL,FLASHWPN,ALM_Q,ALM_S,RESV,RT485; reg [13:0] COUNT; //14bit counter reg [3:0] FLASHAH; reg CLK25,RESET,ALMS,ALMSF,ALMF,ALMQ,RSV; //ALMF decides the frequency of the alarm voice,ALMS acts 1 enable ALM_S wire CSUART; always @(posedge CLK50M or negedge RST_SYSN) //50MHz clock divide begin if ( !RST_SYSN ) begin COUNT <= 0; //clear the counter RESET <= 1; //reset end else begin RESET <= 0; CLK25 <= ~CLK25; //T trigger if ( COUNT[13] && COUNT[12] ) begin ALMSF <= ~ALMSF; COUNT <= 0; end else COUNT <= COUNT + 1; //counter,COUNT[13] is 4.069kHz,for alarm voice end end always @ (CENS[2] or SDWEN) //write CHIP2 triger the special function begin if (~(CENS[2] || SDWEN)) casez ({EA6,EAH}) 5'b0????: FLASHAH <= RESET ? 4'b0000 : EAH;//FLASH space select 5'b10000: ALMS <= 0; //disable alrm voice output 5'b10001: ALMS <= 1 & ( ~RESET ); //enable alrm voice output 5'b10010: ALMQ <= 0; //ALMQ disable 5'b10011: ALMQ <= 1 & ( ~RESET ); //ALMQ enable 5'b10100: RSV <= 0; //reserved output hight 5'B10101: RSV <= 1 & ( ~RESET ); //reserved output low default: FLASHAH <= 0; //select the CODE segment endcase else RSV <= RSV; //NOP end assign FLASHA_H = FLASHAH; //assign WDI = GPIO6; //DSP clear the WatchDogTimer via GPIO6,the signal should be 1 Hz(duty cycle 50%) assign WDI = COUNT[13]; //**************for test assign LEDS[0] = GPIO6; //Heartbeat display(indicates that the system run well) assign LEDS[1] = GPIO7; assign CLK25LXT = CLK25; //25MHz clock for ethernet PHY interface assign CLK25PLL = CLK25; //25MHz clock to PLL device assign TDOEN = ~CENS[0] | CENS[1] | RESET; //enable 3245 when #CHIP1 is slected assign CSFLASHN = EAH[22] | CENS[1] | RESET; //when CHIP1 is selected,and EA[22] acts low,FLASH is accessible assign CSSAN = CENS[1] | ( ~EAH[22] ) | EA6 | RESET; //UART channel A select assign CSSBN = CENS[1] | ( ~EAH[22] ) | (~EA6) | RESET;//UART channel B select //assign EREN = CENS[1] | SDCASN | SDRASN | RESET; //when both #ERE and #AOE act low,FLASH or UART data ouput is enabled assign EREN = CENS[1] | SDRASN | RESET; //when #AOE act low,FLASH or UART data ouput is enable assign EWEN = CENS[1] | SDWEN | RESET; //FLASH and 16c2550 write enable assign REST_DSPN = ~RESET; //DSP can be reseted solely assign REST = RESET; //16C2550 reset assign RESTN = ~RESET; assign GPIO4 = ~INTA; //UART interrupt of channel A assign GPIO5 = ~INTB; //UART interrupt of channel B assign FLASHWPN = ~(CSFLASHN | RESET); //FLASH program protect assign ALM_Q = ALMQ & ( ~RESET ); //alarm output //assign ALM_S = ALMS & GPIO6 & ALMSF; //alarm voice output assign ALM_S = ALMS & (~GPIO6) & ALMSF; //*****************for test assign RESV = RSV & ( ~RESET ); assign RT485 = GPIOH[9] & ( ~RESET ); //1,deliver enable; 0,receive enable endmodule

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非常好，看了特别收益，希望多多出此类作品