Senior Digital Verfication Engineer：工作地点是成都或者新加坡任选其一 1. 5+ experienced ASIC, SOC design verification expert with block to chip level verification experience. Familiar with verification flow and worked on testbench, testplan, test execution and coverage closure, tape out and silicon validation.
2. Hands on experience with one of the modern verification methodologies such as UVM, VMM, OVM, and familiar with constraint random based verification, including OOP, functional coverage, assertion checker/coverage and virtual interface.
3. Proficient in HVL(hardware verification language) such as System Verilog, Verilog, System C or Vera.
4. Knowledge and background in networking protocols such as Ethernet, PCIe, TCP/IP, Serdes, MAC and PHY are preferred.
5. Experience on networking IC design and verification is preferred, especially ethernet switch, PHY, traffic manager, network processor, switch fabric and memory sub system projects.
6. The following skills are not required but under consideration: Perl, TLM, DPI, XACT, XML, PHP, mySQL.
7. Emulation, FPGA verification and IXIA, SmartBit debugging experience are a plus.
提升卡
变色卡
千斤顶
1/9 
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