altera的FIR ip核为什么不能仿真呢?[更新1]

astwyg

altera的FIR ip核为什么不能仿真呢?[更新1] [复制链接]

添加了个FIR的ip核,但是modelsim仿真一直输出都是0,参数设置如下


调用如下
fir50order myFIR(
    .clk(clk),
    .reset_n(rst_n),
    .ast_sink_valid(1'b1),
    .ast_source_ready(1'b1),
    .ast_sink_error(2'b0),
    .ast_sink_data(if_multed[23:12]),
    .ast_source_data(zf_fir)
    );



看了simulation文件夹中rtl_work也一切正常,modelsim也没有报什么奇怪的warning,就是没数据..
请教大牛们,我这问题出哪了?


=================================
附上modelsim控制台输出:
# ** Warning: (vsim-3017) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/pll_10x10m.v(88): [TFMPC] - Too few port connections. Expected 37, found 35.
#
#         Region: /SDR_Platform_vlg_tst/i1/PLL_10X10M_M/altpll_component
# ** Warning: (vsim-3722) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/pll_10x10m.v(88): [TFMPC] - Missing connection for port 'fref'.
#
# ** Warning: (vsim-3722) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/pll_10x10m.v(88): [TFMPC] - Missing connection for port 'icdrclk'.
#
# ** Warning: (vsim-3016) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/mult12x12.v(60): Port type is incompatible with connection (port 'clock').
#
#         Region: /SDR_Platform_vlg_tst/i1/ComplexDDC_12BIT_M/mult12x12_IF_INxcos_I/lpm_mult_component
# ** Warning: (vsim-3016) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/mult12x12.v(60): Port type is incompatible with connection (port 'clock').
#
#         Region: /SDR_Platform_vlg_tst/i1/ComplexDDC_12BIT_M/mult12x12_IF_INxsin_Q/lpm_mult_component
# ** Warning: (vsim-3016) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/mult16x16.v(64): Port type is incompatible with connection (port 'clock').
#
#         Region: /SDR_Platform_vlg_tst/i1/Costas_PD_M/mult16x16_my/lpm_mult_component
# ** Warning: (vsim-3015) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/SDR_Platform.v(323): [PCDPC] - Port size (12 or 12) does not match connection size (14) for port 'if_in'. The port definition is at: E:/loc13/33softwareWireless/DBPSKmoddemod_V11/diff_lpf.v(18).
#
#         Region: /SDR_Platform_vlg_tst/i1/Diff_LPF_Inst
# ** Warning: (vsim-3016) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/mult12x12.v(60): Port type is incompatible with connection (port 'clock').
#
#         Region: /SDR_Platform_vlg_tst/i1/Diff_LPF_Inst/IF_INxIF_DELAY/lpm_mult_component
# ** Warning: (vsim-3017) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/diff_lpf.v(68): [TFMPC] - Too few port connections. Expected 10, found 7.
#
#         Region: /SDR_Platform_vlg_tst/i1/Diff_LPF_Inst/myFIR
# ** Warning: (vsim-3722) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/diff_lpf.v(68): [TFMPC] - Missing connection for port 'ast_sink_ready'.
#
# ** Warning: (vsim-3722) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/diff_lpf.v(68): [TFMPC] - Missing connection for port 'ast_source_error'.
#
# ** Warning: (vsim-3722) E:/loc13/33softwareWireless/DBPSKmoddemod_V11/diff_lpf.v(68): [TFMPC] - Missing connection for port 'ast_source_valid'.
#
#
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run 100 ns
# ** Warning: (vsim-PLI-3407) Too many data words read on line 127500 of file "BPSK_data.txt". (Current address [127501], address range [1:127500])    : E:/loc13/33softwareWireless/DBPSKmoddemod_V11/simulation/modelsim/SDR_Platform.vt(74)
#    Time: 0 ps  Iteration: 0  Instance: /SDR_Platform_vlg_tst
#  Note : Cyclone II PLL is enabled
# Time: 0  Instance: SDR_Platform_vlg_tst.i1.PLL_10X10M_M.altpll_component.stratixii_pll.pll1
# Warning : Invalid transition to 'X' detected on StratixII PLL input clk. This edge will be ignored.

===2013年12月20日 10:40:36追加===
之前的问题被解决,参数和配置没有问题,错误有两个可能性:
一是rst正负极接反了,这个肯定是错了..
二是需要把所有input都接上,这个不确定是不是所有的,至少目前都接上是可以用的,稍后有时间会排查下.

图补上:



现在还有俩问题,
一是为嘛加上这个fir模块以后仿真变得超级慢,绝对不是心理作用,确实是超级慢了.看手册没有指出来哪里能修改仿真速度,TestBench精度是没变的,这个不知道能不能解决.
二是是不是FIR2这个ip核只能用file来输入滤波器参数?FIR和FIR2有什么区别么?除了构建时候的形式.

[ 本帖最后由 astwyg 于 2013-12-20 10:46 编辑 ]

astwyg

再追加一点:
生成FIR ip核以后需要手动把.vo文件拷贝到modelsim文件夹下,然后再编译一次项目,否则会报错让你看.rpt文件,log大意是使用的ip核过旧.

FIR ip核是需要额外破解的,破解方法发个链接:
http://blog.sina.com.cn/s/blog_9cf88b750101ej1t.html

hgbest

后面我也出现了你的那个问题输出全为0，也不知道是不是配置错了

寒剑孤影

可以自己写个testbench，仿真一下，更能够了解IP核的使用。好像只能进行时序仿真，RTL级的不行！