Testbench

火箭_1991

Testbench [复制链接]

//testbench for vgasdram
`timescale 1ns/1ns
module tb_m4kram;
reg clk;  //系统时钟，50MHz
reg rst_n;  //复位信号，低电平有效
reg wren;   //RAM写入使能信号，高表示写入
reg[11:0] addrin; //RAM地址总线
reg[7:0]  datain; //RAM写入数据总线
wire[7:0] datout;  //RAM读出数据总线
M4K m4k(
      .clk(clk),
      .rst_n(rst_n),
      .datout(datout),
      .wren(wren),
      .addrin(addrin),
      .datain(datain)
    );

initial begin
  rst_n = 0;
  wren = 0;
  addrin = 12'hzzz;
  datain = 8'hzz;
  #200;
  rst_n = 1;
  
  #30; //delay 3us
  
  task_wr_ram(12'd0,8'd0); //0地址写数据0
  task_wr_ram(12'd1,8'd1); //1地址写数据1
  task_wr_ram(12'd2,8'd2); //2地址写数据2
  task_wr_ram(12'd3,8'd3); //3地址写数据3
  
  @(posedge clk);
  addrin = 12'd0; //读0地址
  @(posedge clk);
  addrin = 12'd0; //读1地址
  @(posedge clk);
  addrin = 12'd1; //读2地址
  @(posedge clk);
  addrin = 12'd1; //读3地址
  
  #100;
  $stop;
end
initial begin
  clk = 0;
  forever
  #5 clk = ~clk;
end

//写入RAM任务
task task_wr_ram;
  input[11:0] t_addr;
  input[7:0] t_data;
  begin
    @(posedge clk);
    fork
    wren = 1;
    addrin = t_addr;
    datain = t_data;
    join
    @(posedge clk);
    fork
    wren = 0;
    addrin = 12'hzzz;
    datain = 8'hzz;
    join  
  end
endtask
endmodule

对initiall 模块不是很理解
task_wr_ram(12'd0,8'd0); //0地址写数据0
  task_wr_ram(12'd1,8'd1); //1地址写数据1
  task_wr_ram(12'd2,8'd2); //2地址写数据2
  task_wr_ram(12'd3,8'd3); //3地址写数据3
@(posedge clk);
  addrin = 12'd0; //读0地址
  @(posedge clk);
  addrin = 12'd0; //读1地址
  @(posedge clk);
  addrin = 12'd1; //读2地址
  @(posedge clk);
  addrin = 12'd1; //读3地址
这8条语句是顺序执行的么，@(poseedge clk ) 怎么理解？

该testbench 来源于特权同学的《深入浅出玩转FPGA》

zhuoyue

深入浅出玩转FPGA，想要自学真不容易