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回复 9楼 destinydd 的帖子
其实就把上面帖子改下
//CE -- P2.0 ; CSN --- P2.1 ; IRQ --- P2.2
//SCLK --- P1.5 ; MISO --- P1.6 ; MOSI --- P1.7
//上一行引脚可以自选
//下一行引脚必须对应
void SPI_IO_Init(void)
{
P1DIR |= BIT(CLK) + BIT(MOSI);
P2DIR |= BIT(CSN) + BIT(CE); //output
/*设置NRF24L01 中断
P2DIR &= ~(BIT(IRQ)); //set P2.2 is input
P2IE |= BIT(IRQ); //allow P2.2 IQR
P2IES |= BIT(IRQ);
P2IFG = 0x00; //清除中断标志位*/
P2OUT &= ~BIT(CE); //CHIP DISABLE
P2OUT |= BIT(CSN); //CSN IS PULL HIGH.DISABLE THE OPERATION
P1SEL |= BIT(CLK) + BIT(MOSI) + BIT(MISO);
P1SEL2 |= BIT(CLK) + BIT(MOSI) + BIT(MISO);
UCB0CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC; // 3-pin, 8-bit SPI master
UCB0CTL1 |= UCSSEL_2; // UCSSEL_2=0x80 -- SMCLK
UCB0BR0 |= 0x02; // /2
UCB0BR1 = 0; // 位速率控制
// UCB0MCTL = 0; // No modulation
UCB0CTL1 &= ~UCSWRST;
} |
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