【设计工具】使用retiming提高FPGA性能

sdjntl

【设计工具】使用retiming提高FPGA性能 [复制链接]

Retiming is an intelligent process of moving and balancing registers backward and/or forward across combinatorial delay paths to obtain an optimum timing while maintaining the functional behavior of the circuit. As describing by a well-known author, Leiserson and Saxe [1], retiming algorithm can find an optimum solution for clock period when the circuit is timed by one clock on the same edge without considering interconnect delay. A flip-flop can be moved from each incoming edge of a combinational component to each of the outgoing edges of the component. Such a move can reduce the critical path delay associated with the flip-flop. However, it can move across only one combinatorial component each time, so the timing improvement offered by this algorithm is very limited. Also there are numerous limitations concerning interconnect delay and packing rules for each specific FPGA architecture technology. The current retiming algorithms developed by today’s FPGA synthesis tools are working towards solving and enhancing these limitations to obtain a much better timing performance.
Pipelining is another optimization technique that involves partitioning logic into stages so that the first stage can begin processing new inputs while the last stage is finishing the previous inputs. This ensures better throughput and faster circuit performance. For pipelining, some synthesis tools may actually introduce more registers in a cycle or delay path from a primary input to primary output pins therefore adding clock latency cycles to the designs.

eeleader

感谢，太好了！