quartus ii9.0中怎么看哪些寄存器被综合掉了，特权大哥的johnson

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quartus ii9.0中怎么看哪些寄存器被综合掉了，特权大哥的johnson [复制链接]

试验中大家注意看rtl代码没，我根据他视频写的程序，一些寄存器没有了，用网上的方法没作用，在综合报告中也没看到
代码如下：
module ledflow(
clk,rst_n,
led,s1_n,s2_n,s3_n);
input clk; //时钟信号
input rst_n; //复位信号
output[3:0] led; //二极管0显示
input s1_n,s2_n,s3_n; //3个独立按键

reg led_dir ; //1'b1:low to high 1'b0:high to low
reg led_on ; //1'b1:on 1'b0:off
//------------------------------------------------------------
reg[23:0] cnt;
always @ (posedge clk or negedge rst_n)
if(!rst_n) cnt <= 24'd0;
else cnt <= cnt + 1'b1;

//--------------------------------------------------------------
reg[3:0] led_r;
always @ (posedge clk or negedge rst_n)
if(!rst_n) led_r <= 4'b0001;
else if(cnt == 24'hfffffe && led_on)
begin
if(led_dir) led_r <= {led[2:0],led[3]}; //low to high
else    led_r <= {led[0],led[3:1]}; //high to low
end
assign led = led_r;

/***********************************************************************\

         the code blow is for keyboard scan

\***********************************************************************/

reg[2:0] key_rst /* synthesis preserve */;
always @ (posedge clk or negedge rst_n)
if(!rst_n) key_rst <= 3'b111;
else key_rst <= {s3_n,s2_n,s1_n};

//-----------------------------------------------------------------
reg[2:0] key_rst_r /* synthesis preserve */;
always @ (posedge clk or negedge rst_n)
if(!rst_n) key_rst_r <= 3'b111;
else key_rst_r <= key_rst;

//当key_rst由1变成0时，led_an的值由低变高，维持一个时钟周期
wire[2:0] key_an = key_rst_r & (~key_rst);
//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
reg[19:0] count/* synthesis preserve */;
always @ (posedge clk or negedge rst_n)
if(!rst_n) count <= 20'd0;
else if(key_an) count <= 20'd0;
else count <= count + 1'b1;

reg[2:0] low_sw;
always @ (posedge clk or negedge rst_n)
if(!rst_n) low_sw <= 3'b111;
else if(cnt == 20'hfffff)
low_sw <= {s3_n,s2_n,s1_n};

/*******************************************************************************/
reg[2:0] low_sw_r;
always @ (posedge clk or negedge rst_n)
if(!rst_n) low_sw_r <= 3'b111;
else low_sw_r <= low_sw;
//当寄存器low_w由1变成0时，led_ctrl的值变为高，维持一个时钟周期
wire[2:0] led_ctrl = low_sw_r[2:0] & (~low_sw[2:0]);

//=============================================================================
always @ (posedge clk or negedge rst_n)
if(!rst_n) begin //按键值初始化
led_on = 1'b1;
led_dir= 1'b0;
end
else begin    //
if(led_ctrl[0]) led_on <= ~led_on;
if(led_ctrl[1]) led_dir <= 1'b0;
if(led_ctrl[2]) led_dir <= 1'b1;
end
endmodule

rtl图如下