|
在 71x_init.s 中设置时钟
//------------------------------------------------------------------------------ // Setup MCLK/PCLK/FCLK = 48/24/24 MHz - External Clk is 4MHz //------------------------------------------------------------------------------ LDR R1,=0x101 //PCU->PDIVR = 0x00000101 LDR R0,=0xA0000044 //PCLK1 = 48MHz / 2 = 24MHz STRH R1,[R0,#0x0] //PCLK2 = 48MHz / 2 = 24MHz MOV R1,#0x60 // 4/2 *24 /1 = 48MHz LDR R0,=0xA0000018 STR R1,[R0,#0x0] MOV R0,#0xA0000008 //while(!(RCCU->CFR & RCCU_LOCK_Mask)) WAIT_LOCK LDR R1,[R0,#0x0] TST R1,#0x0002 BEQ WAIT_LOCK
LDR R1,=0x800B //RCCU->CFR = 0x0000800B// STR R1,[R0,#0x0]
//------------------------------------------------------------------------------ // Setup USB_CLK //------------------------------------------------------------------------------ // Configure the PLL2 ( * 12 , / 1 ) assuming HCLK=4MHz // 48MHz for USB is Enable //------------------------------------------------------------------------------
LDR R1,=0x000000E8 //USBEN PLL2EN *12 /1 LSL R1, R1, #1 LDR R0,=0xA000004C STRH R1, [R0, #0x0] //PCD_PLL2CR = 0x000001D0
WAIT_LOCK2 LDR R1,[R0,#0x0] TST R1,#0x8000 BEQ WAIT_LOCK2 |
|