利用iiC对芯片寄存器配置，仿真有问题，望高手指点

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利用iiC对芯片寄存器配置，仿真有问题，望高手指点 [复制链接]

////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
module iic(rst,clk,outdata,scl,sda,rst_out);

input rst;
input clk;
output outdata;
output scl;
inout sda;
output rst_out; //the rst bit of the 371

//////////////////////////////////////////////////e
reg rst_out_r;

reg[7:0] j;
reg sense_r;

reg[7:0] reg_add_tmp;
reg[7:0] indata;
reg read_or_write;

parameter cap_config=8'b0000_0000;
parameter int_config1= 8'b1100_0100;
parameter int_config2=8'b0000_1001;
parameter ctrl_config= 8'b0000_0001;

assign rst_out = rst_out_r;
////////////////////////////////////////////
wire ack_out;

reg[9:0] cnt_10us;
reg[7:0] add1;
reg[7:0] add2;

always @ (posedge clk or negedge rst)
begin
if(!rst) cnt_10us <= 5'd0;
else cnt_10us <= cnt_10us+1'b1;
end

always@( ack_out or rst)
begin
if(!rst)
begin
  rst_out_r<=1'b0;
  read_or_write<=1'b0;
  add1<=8'd4;
  add2<=8'd46;
  indata<=cap_config;
  sense_r<=1'b0;
  j<=8'd2;
  reg_add_tmp<=8'b0000_0110;//?
end

else if(cnt_10us==10'd500) rst_out_r<=1'b1;
else if((j<=8'd5)&&(j>=8'd2))
  begin
   read_or_write<=0;
   reg_add_tmp<=add1+j;
   indata<=cap_config;
  end
else if((j<=8'd13)&&(j>=8'd6))
  begin
   read_or_write<=0;
   reg_add_tmp<=add1+j;
   if((j%8'd2)==0)
    indata<=int_config1;
    else indata<=int_config2;
  end
else if(j==8'd14)
  begin
   read_or_write<=0;
   reg_add_tmp<=8'd1;
   indata<=ctrl_config;
  end
else if(j==8'd15)
  begin
   read_or_write<=0;
   reg_add_tmp<=8'd0;
   indata<=ctrl_config;
  end
else if((j>=8'd16)&&(j<=8'd23))
  begin
   read_or_write<=1;
   reg_add_tmp<=add2+j;
  end
else j<=8'd16;
j<=j+8'd1;
sense_r<=~sense_r;
end

///////////////////////////////////////////
reg[4:0] k;
reg outdata_r;
always @ (posedge clk or negedge rst)
begin
if(!rst)outdata_r<=0;
else
  for(k=0;k<=7;k=k+1)
   begin
    outdata_r<=read_data[k];
   if(k==8) k<=0;
   end
end
assign outdata = outdata_r;

wire[8:0] read_data;
//////////////////////////////////////////
iic_com iic_com(     .read_or_write(read_or_write),
       .reg_add(reg_add_tmp),
       .write_data(indata),
       .clk(clk),
       .rst(rst),
       .scl(scl),
       .sda(sda),
       .ack_out(ack_out),
       .outdata(read_data)
       );
endmodule