warning该如何解决？

eeleader

warning该如何解决？ [复制链接]

1.Warning (10272): Verilog HDL Case Statement warning at usb.v(86): case item expression covers a value already covered by a previous case item

2.Warning (10235): Verilog HDL Always Construct warning at usb.v(72): variable "readMem" is read inside the Always Construct but isn't in the Always Construct's Event Control

3.Warning: Using design file fifo1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project（fifo1是文中的一相FIFO模块，fifo1.v应该是自动产生的）

4.Warning: The following nodes have both tri-state and non-tri-state drivers
Warning: TRI or OPNDRN buffers permanently enabled
Warning: Following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results（这三个都是关于FD［15：0］，这个数据线reg型，inout型。）

baiyefengqi

第二条是指你这个变量不是事件触发型的