post-map simulation过程中出现的$setup问题

eeleader-mcu

post-map simulation过程中出现的$setup问题 [复制链接]

做后仿真，到post-map simulation这步的时候，在ISE中Map到是通过了的，但是当调用ModelSim仿真的时候出现了一堆下面的问题，实在是不知道怎么查找问题所在了，发上来寻找帮助。
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_0\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_1\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_2\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_3\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_18\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_26\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_19\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_27\
# ** Error: C:/Modeltech_6.2b/xilinx_libs/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):111443 ps, posedge CLK:111908 ps, 852 ps );
#    Time: 111908 ps  Iteration: 0  Instance: /cor_estimate_vtf_v/uut/\freq2fcw_top_u/freq2fcw_u/fcw_out_28\
不知道上述错误是由于什么原因引起的，因此不知道从何排查，望大家指点一下啊。:(

eeleader

问题一样：

 

没有采用全同步设计，造成采样沿建立时间不够！