自己写的johnson计数器出问题了

heningbo

自己写的johnson计数器出问题了 [复制链接]

代码如下：

module johnson (clk,rst_n,sw1,sw2,sw3,led);
 input clk,rst_n;
 input sw1,sw2,sw3;
 output [3:0] led;
 reg [3:0] led;
 //-----------------------------------------
 reg[23:0] cnt1;
 always @(posedge clk or negedge rst_n)
  begin
   if (!rst_n) cnt1<=20'b0;
   else cnt1 <= cnt1+1'b1;
  end
 //-----------------------------------------
 always @(posedge clk or negedge rst_n)
  begin
   if    (!rst_n) led <= 3'b001;
   else  if (cnt1==24'hffffff && d1)
     begin
     if(d2)
        led<={led[0],led[3:1]};
              else if (d3)
     led<={led[2:0],led[3]};
     end
  end
 //-----------------------------------------
 reg [2:0] sw_rst;
 always @(posedge clk or negedge rst_n)
  begin
   if (!rst_n) sw_rst<=3'b111;
   else sw_rst<={sw3,sw2,sw1};
  end
 //-----------------------------------------
 reg[2:0] sw_rst_r;
 always @(posedge clk or negedge rst_n)
  begin
   if (!rst_n) sw_rst_r <= 3'b111;
   else sw_rst_r <= sw_rst;
  end
 //-----------------------------------------
 wire [2:0]sw_an =sw_rst_r & (~sw_rst);
 //-----------------------------------------
 reg[19:0] cnt;
 always @(posedge clk or negedge rst_n)
  begin
   if (!rst_n) cnt<=20'b0;
   else if   (sw_an) cnt<=20'b0;
     else cnt <= cnt+1'b1;
  end
 //-----------------------------------------
 reg[2:0] low_sw;
 always @(posedge clk or negedge rst_n)
  begin
   if   (!rst_n) low_sw<=3'b111;
   else if(cnt==20'hfffff)
     low_sw <={sw3,sw2,sw1};
     else
     low_sw<=low_sw;
  end
 //-----------------------------------------
 reg[2:0] low_sw_r;
 always @(posedge clk or negedge rst_n)
  begin
   if   (!rst_n) low_sw_r<=3'b111;
   else low_sw_r<=low_sw;
  end
 //-----------------------------------------
 wire [2:0] led_ctrl =low_sw_r & (~low_sw);
 //-----------------------------------------
 reg d1;
 reg d2;
 reg d3;
 always @(posedge clk or negedge rst_n)
   if   (!rst_n) begin
       d1<=1'b0;
       d2<=1'b0;
       d3<=1'b0;
        end
      else  begin
    if (led_ctrl[0])  d1<=~d1;
    if (led_ctrl[1])  d2<=~d2;
    if (led_ctrl[2])  d3<=~d3;
     end
endmodule

heningbo

关键是如果我将：
always @(posedge clk or negedge rst_n)
  begin
   if    (!rst_n) led <= 3'b001;
   else  if (cnt1==24'hffffff && d1)
     begin
     if(d2)
        led<={led[0],led[3:1]};
              else if (d3)
     led<={led[2:0],led[3]};
     end
  end
写成：
always @(posedge clk or negedge rst_n)
  begin
   if    (!rst_n) led <= 3'b001;
   else  if (cnt1==24'hffffff && led_ctrl【0】)
     begin
     if(led_ctrl【1】)
        led<={led[0],led[3:1]};
              else if led_(ctrl【2】)
     led<={led[2:0],led[3]};
     end
  end
程序就有问题