顶层模块为——
module ramout( input clkin, input [7:0] addr_read, output [11:0] data_read );
reg [ 7:0] cnt; reg [ 1:0] status;
reg [ 7:0] addr; reg [15:0] din; wire [15:0] dout; reg we;
paremeter step = 16'd1; //只要不是1就报错
parameter size1 = 8‘d166;
assign data_read = dout[11:0];
ram1 ram11(.addr(addr), .clk(clkin), .din(din), .dout(dout), .we(we) );
always@(negedge clkin) if(cnt != size1) cnt <= cnt + 8'd1;
always@(negedge clkin) if(cnt < 8'd6) status <= 2'd0; else if(cnt != size1) begin status <= 2'd1; we <= 1'b1; din <= din + 16'd1;
addr <= addr + 8'd1; end else begin status <= 2'd2; we <= 1'b0; end
always@(negedge clkin) if(status == 2'd2 && addr_read < size1) addr <= addr_read;
endmodule
step为1时不报错,为2或3就报错——
ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr_cy<0>> ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr2> ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr4> ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr6> ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr8> ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr10> ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr12> ERROR:Xst:528 - Multi-source in Unit <myad> on signal <Mcount_addr14>
我的片上存储器的宽度为16位,深度为256。
为什么?
先谢过!
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