verilog assign语句的用法1

eeleader-mcu

verilog assign语句的用法1 [复制链接]

 

（1）module assign_test (

                       clk,

                       lhold,

                       lholda

                   );

 

input clk;

input lhold;

output lholda;

 

reg lholda;

      always @(posedge clk)

            if (lhold)

               lholda<=lhold;

            else

               lholda<=0;

 

endmodule

 

wugang123

好像没有区别啊！！！

chinatiger11

看起来确实没区别哦