这个是我把100MHZ的分成10MHZ的程序 我想把修改下 能把2MHZ的分成1HZ的 望各位指教
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity df is
port (reset : in std_logic;
clk_in: in std_logic;
clk_out: out std_logic);
end df;
architecture cc of df is
signal clk_cnt : unsigned(3 downto 0);
signal clk_bit : std_logic;
begin
process(clk_in,reset)
begin
if(reset='1') then
clk_cnt<="0000";
clk_bit<='0';
elsif rising_edge(clk_in) then
if (clk_cnt=4) then
clk_cnt<="0000";
clk_bit<=not clk_bit;
else
clk_cnt<= clk_cnt+1;
end if;
end if;
end process;
clk_out<=clk_bit;
end cc;
2M_1hz_cnt : process (rst, ck_2m)
if (rst = '1') then
ck_2m_1hz_cnt <= (others => '0');
elsif (ck_2m'event and ck_2m = '1') then
if (ck_2m_1hz_cnt < 16#F4240#) then -- 2M clock 100000 分频
ck_2m_1hz_cnt <= ck_2m_1hz_cnt + 1;
else
ck_2m_1hz_cnt <= (others => '0');
end if;
end if;
end process;
2M_1hz : process(ck_2m_1hz_cnt, rst)
begin
if (rst='1') then
clk_1hz <= '0';
elsif (ck_2m_1hz_cnt = 16#F4240#) then
clk_1hz <= not clk_1hz;
end if;
end process;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY count_60 IS
PORT(CLRN,CLK : IN STD_LOGIC;
segout : OUT std_logic_vector(6 DOWNTO 0);
scan1,scan2,scan3,scan4,scan5,scan6,scan7,scan8 : out std_logic ) ;
END count_60;
ARCHITECTURE a OF count_60 IS
type state is (S00,S01,S02,S03,S04,S05,S06,S07);
signal state_machine1 : state;
signal Qh2,Qh1,Qm2,Qm1,Qs2,Qs1,Qout :STD_LOGIC_VECTOR(3 downto 0);
signal Qclk :STD_LOGIC;
signal count:STD_LOGIC_VECTOR(9 downto 0);
BEGIN
//这就是分频进程,你可以看一下这是1000分频,2MHZ分频即把1111101000改为11110100001001000000同时改变qclk<=count(19)。我认为理解画出脉冲图有助于理解分频,周期的可以从图中读出。其他的方法楼上几位也说了,我只是提出z自己的一点小心得,希望对你有些帮助。
process(clk)
begin
if rising_edge(clk) then
if count="1111101000" then count<="0000000000";
else
count<=count+1;
end if;
end if;
qclk<=count(9);
end process;
PROCESS (qClk)
VARIABLE tmph2 :STD_LOGIC_VECTOR(3 downto 0);
VARIABLE tmph1 :STD_LOGIC_VECTOR(3 downto 0);
VARIABLE tmpm2 :STD_LOGIC_VECTOR(3 downto 0);
VARIABLE tmpm1 :STD_LOGIC_VECTOR(3 downto 0);
VARIABLE tmps2 :STD_LOGIC_VECTOR(3 downto 0);
VARIABLE tmps1 :STD_LOGIC_VECTOR(3 downto 0);
BEGIN
IF CLRN='0' THEN tmph2 := "0000";
tmph1 := "0000";
tmpm2 := "0000";
tmpm1 := "0000";
tmps2 := "0000";
tmps1 := "0000";
ELSE
IF (qClk'event AND qClk='1') THEN
IF ((tmps1="0100"and tmps2="0010")or tmps1="1001") THEN tmps1:="0000";
IF tmps2="0010" THEN tmps2:="0000";
IF ((tmpm1="0100"and tmpm2="0010")or tmpm1="1001") THEN tmpm1:="0000";
IF tmpm2="0010" THEN tmpm2:="0000";
IF ((tmph1="0100"and tmph2="0010")or tmph1="1001") THEN tmph1:="0000";
IF tmph2="0010" THEN tmph2:="0000";
ELSE tmph2:= tmph2+1;
END IF;
ELSE tmph1 := tmph1+1;
END IF;
ELSE tmpm2 := tmpm2+1;
END IF;
ELSE tmpm1 := tmpm1+1;
END IF;
ELSE tmps2 := tmps2+1;
END IF;
ELSE tmps1 := tmps1+1;
END IF;
END IF;
END IF;
state_machine1 <= S06;
when S06=>
Qout <=Qh1; --显示数字1,片选高电平有效
scan1<= '0';scan2 <= '1';scan3<= '0';scan4<= '0';
scan5<= '0';scan6 <= '0';scan7<= '0';scan8<= '0';
state_machine1 <= S07;
when S07=>
Qout <=Qh2; --显示数字1,片选高电平有效
scan1<= '1';scan2 <= '0';scan3<= '0';scan4<= '0';
scan5<= '0';scan6 <= '0';scan7<= '0';scan8<= '0';
state_machine1 <= S00;
when others=> state_machine1 <=s00; --错误,重新开始
end case;
end if;
end process;
WITH Qout SELECT
segout <= "1111110" WHEN "0000",
"0110000" WHEN "0001",
"1101101" WHEN "0010",
"1111001" WHEN "0011",
"0110011" WHEN "0100",
"1011011" WHEN "0101",
"1011111" WHEN "0110",
"1110000" WHEN "0111",
"1111111" WHEN "1000",
"1111011" WHEN "1001",
"0000001" WHEN "1111",
"-------" WHEN OTHERS;
END a;