DM642EVM的BSL源代码

Aguilera

DM642EVM的BSL源代码 [复制链接]

本帖最后由 Aguilera 于 2019-2-11 22:57 编辑

/*  All rights reserved. Property of Spectrum Digital Incorporated. */

/*
*  ======== evmdm642.c ========
*  EVMDM642 board initializion implementation.
*/

#include
#include
#include
#include
#include

#include "evmdm642.h"
#include "evmdm642_apll.h"

/* I2C handle */
I2C_Handle EVMDM642_I2C_hI2C;

/* GPIO handle */
GPIO_Handle EVMDM642_GPIO_hGPIO;

/* Initialize the board APIs */
void EVMDM642_init()
{
volatile Uint32 test;

EMIFA_Config emifaCfg0 = {
      EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK) |
      EMIFA_FMKS(GBLCTL, EK2HZ, CLK)       |
      EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)    |
      EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS) |
      EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)    |
      EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)       |
      EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)    |
      EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE)    |
      EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),

      EMIFA_FMKS(CECTL, WRSETUP, DEFAULT) |
      EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)    |
      EMIFA_FMKS(CECTL, WRHLD, DEFAULT)    |
      EMIFA_FMKS(CECTL, RDSETUP, DEFAULT) |
      EMIFA_FMKS(CECTL, TA, DEFAULT)       |
      EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)    |
      EMIFA_FMKS(CECTL, MTYPE, SDRAM64)    |
      EMIFA_FMKS(CECTL, RDHLD, DEFAULT),

      EMIFA_FMKS(CECTL, WRSETUP, OF(7))    |
      EMIFA_FMKS(CECTL, WRSTRB, OF(14))    |
      EMIFA_FMKS(CECTL, WRHLD, OF(2))       |
      EMIFA_FMKS(CECTL, RDSETUP, OF(2))    |
      EMIFA_FMKS(CECTL, TA, OF(2))          |
      EMIFA_FMKS(CECTL, RDSTRB, OF(14))    |
      EMIFA_FMKS(CECTL, MTYPE, ASYNC8)    |
      EMIFA_FMKS(CECTL, RDHLD, OF(1)),

      EMIFA_FMKS(CECTL, WRSETUP, OF(2))    |
      EMIFA_FMKS(CECTL, WRSTRB, OF(10))    |
      EMIFA_FMKS(CECTL, WRHLD, OF(2))       |
      EMIFA_FMKS(CECTL, RDSETUP, OF(2))    |
      EMIFA_FMKS(CECTL, TA, OF(2))          |
      EMIFA_FMKS(CECTL, RDSTRB, OF(10))    |
      EMIFA_FMKS(CECTL, MTYPE, ASYNC32)    |
      EMIFA_FMKS(CECTL, RDHLD, OF(2)),

      EMIFA_FMKS(CECTL, WRSETUP, OF(2))    |
      EMIFA_FMKS(CECTL, WRSTRB, OF(10))    |
      EMIFA_FMKS(CECTL, WRHLD, OF(2))       |
      EMIFA_FMKS(CECTL, RDSETUP, OF(2))    |
      EMIFA_FMKS(CECTL, TA, OF(2))          |
      EMIFA_FMKS(CECTL, RDSTRB, OF(10))    |
      EMIFA_FMKS(CECTL, MTYPE, SYNC32)    |
      EMIFA_FMKS(CECTL, RDHLD, OF(2)),

      EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)    |
      EMIFA_FMKS(SDCTL, SDRSZ, 12ROW)       |
      EMIFA_FMKS(SDCTL, SDCSZ, 8COL)       |
      EMIFA_FMKS(SDCTL, RFEN, ENABLE)       |
      EMIFA_FMKS(SDCTL, INIT, YES)          |
      EMIFA_FMKS(SDCTL, TRCD, OF(1))       |
      EMIFA_FMKS(SDCTL, TRP, OF(1))       |
      EMIFA_FMKS(SDCTL, TRC, OF(5))       |
      EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),

      EMIFA_FMKS(SDTIM, XRFR, OF(0))       |
      EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),

      EMIFA_FMKS(SDEXT, WR2RD, OF(1))       |
      EMIFA_FMKS(SDEXT, WR2DEAC, OF(3))    |
      EMIFA_FMKS(SDEXT, WR2WR, OF(1))       |
      EMIFA_FMKS(SDEXT, R2WDQM, OF(3))    |
      EMIFA_FMKS(SDEXT, RD2WR, OF(2))       |
      EMIFA_FMKS(SDEXT, RD2DEAC, OF(3))    |
      EMIFA_FMKS(SDEXT, RD2RD, OF(1))       |
      EMIFA_FMKS(SDEXT, THZP, OF(2))       |
      EMIFA_FMKS(SDEXT, TWR, OF(2))       |
      EMIFA_FMKS(SDEXT, TRRD, OF(0))       |
      EMIFA_FMKS(SDEXT, TRAS, OF(6))       |
      EMIFA_FMKS(SDEXT, TCL, OF(1)),

      EMIFA_CESEC_DEFAULT,

      EMIFA_CESEC_DEFAULT,

      EMIFA_CESEC_DEFAULT,

      EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2) |
      EMIFA_FMKS(CESEC, RENEN, READ)       |
      EMIFA_FMKS(CESEC, CEEXT, ACTIVE)    |
      EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE)    |
      EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
};

I2C_Config i2cCfg = {
      0x0000007f, /* I2COAR - Not used if master */
      0x00000000, /* I2CIER - Disable interrupts, use polling */
      0x0000001b, /* I2CCLKL - Low period for 100KHz operation */
      0x0000001b, /* I2CCLKH - High period for 100KHz operation */
      0x00000002, /* I2CCNT - Data words per transmission */
      0x0000001a, /* I2CSAR - Slave address */
      0x00004680, /* I2CMDR - Mode */
      0x00000019  /* I2CPSC - Prescale 300MHz to 12MHz */
};

/* Initialize CSL */
CSL_init();

/* Unlock PERCFG through PCFGLOCK */
*((unsigned long *)0x1b3f018) = 0x10c0010c;

/* Enable VP0-VP2, I2C and McASP0 in PERCFG */
*((unsigned long *)0x1b3f000) = 0x79;

/* Read back PERCFG */
test = *((unsigned long *)0x1b3f000);

/* Wait at least 128 CPU cycles */
EVMDM642_wait(128);

/* Initialize EMIFA */
EMIFA_config(&emifaCfg0);

/* Open I2C handle */
EVMDM642_I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET);

/* Configure I2C controller */
I2C_config(EVMDM642_I2C_hI2C, &i2cCfg);

/* Take I2C out of reset */
I2C_outOfReset(EVMDM642_I2C_hI2C);

/* Open the GPIO handle */
EVMDM642_GPIO_hGPIO = GPIO_open(GPIO_DEV0, GPIO_OPEN_RESET);

/* Enable caching of SDRAM */
CACHE_enableCaching(CACHE_EMIFA_CE00);
CACHE_enableCaching(CACHE_EMIFA_CE01);

/* Load the FPGA from Flash */
EVMDM642_fpgaLoad(EVMDM642_FPGAFLASH_BASE);

/* Configure APLL in default state */
EVMDM642_APLL_rset(EVMDM642_APLL_FSG0);
}

/* Read an 8-bit value from a CPLD register */
Uint8 EVMDM642_rget(Int16 regnum)
{
Uint8 *pdata;

/* Return lower 8 bits of register */
pdata = (Uint8 *)(EVMDM642_CPLD_BASE + regnum);
return (*pdata & 0xff);
}

/* Write an 8-bit value to a CPLD register */
void EVMDM642_rset(Int16 regnum, Uint8 regval)
{
Uint8 *pdata;

/* Write lower 8 bits of register */
pdata = (Uint8 *)(EVMDM642_CPLD_BASE + regnum);
*pdata = (regval & 0xff);
}

/* Spin in a delay loop for delay iterations */
void EVMDM642_wait(Uint32 delay)
{
volatile Uint32 i, n;

n = 0;
for (i = 0; i < delay; i++)
{
      n = n + 1;
}
}

/* Spin in a delay loop for delay microseconds */
void EVMDM642_waitusec(Uint32 delay)
{
EVMDM642_wait(delay * 21);
}

/*
*  Copyright 2003 by Spectrum Digital Incorporated.
*  All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
*  ======== evmdm642_aic23_loopback.c ========
*  EVMDM642_AIC23_loopback() implementation
*/

#include
#include

/*
*  ======== EVMDM642_AIC23_loopback ========
*  Enable/disable codec loopback mode
*/
void EVMDM642_AIC23_loopback(EVMDM642_AIC23_CodecHandle hCodec, Int16 mode)
{
int regval;

/* Set bypass bit if mode is true */
regval = (mode) ? 0x8 : 0x0;

/* Write to codec register */
EVMDM642_AIC23_rset(hCodec, EVMDM642_AIC23_ANAPATH,
      (EVMDM642_AIC23_rget(hCodec, EVMDM642_AIC23_ANAPATH) & 0xfff7 | regval));
}

/*
*  Copyright 2003 by Spectrum Digital Incorporated.
*  All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
*  ======== evmdm642_aic23_mute.c ========
*  EVMDM642_AIC23_mute() implementation
*/

#include
#include

/*
*  ======== EVMDM642_AIC23_mute ========
*  Enable/disable codec mute mode
*/
void EVMDM642_AIC23_mute(EVMDM642_AIC23_CodecHandle hCodec, Int16 mode)
{
int regval;

/* Enable mute if mode is true */
regval = (mode) ? 0x08 : 0x00;

/* Write to codec registers (left and right) */
EVMDM642_AIC23_rset(hCodec, EVMDM642_AIC23_DIGPATH,
      (EVMDM642_AIC23_rget(hCodec, EVMDM642_AIC23_DIGPATH) & 0xfff7) | regval);
}

evmdm642_aic23_opencodec.c

/*
*  Copyright 2003 by Spectrum Digital Incorporated.
*  All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
*  ======== evmdm642_aic23_openCodec.c ========
*  EVMDM642_AIC23_openCodec() implementation
*/

#include
#include
#include
#include
#include

/* AIC23 handles */
MCASP_Handle EVMDM642_AIC23_hMcASP;

MCASP_ConfigGbl mcaspCfgDataGbl = {
0x00000000, /* PFUNC -    All pins as McASP */
0x00000001, /* PDIR  -    XMT DATA output, rest are inputs */
0x00000000, /* DITCTL - DIT mode disable */
0x00000000, /* DLBCTL - Loopback disabled */
0x00000000  /* AMUTE  - Never drive AMUTE */
};

MCASP_ConfigRcv mcaspCfgDataRcv = {
0xffffffff, /* RMASK -    Use all 32 bits */
0x000080f8, /* RFMT -    MSB first, 32-bit slots, CPU bus, 0 bit delay */
0x00000000, /* AFSRCTL - burst, single bit frame sync, ext FS */
0x00000080, /* ACLKRCTL -  Sample on rising CLK, divide by 1, ext CLK */
0x00000000, /* AHCLKRCTL - External HCLK */
0x00000001, /* RTDM -    Slots 0-31 are active */
0x00000000, /* RINTCTL - No interrupts */
0x00000000  /* RCLKCHK - Not used */
};

MCASP_ConfigXmt mcaspCfgDataXmt = {
0xffffffff, /* XMASK -    Use all 32 bits */
0x000080f8, /* XFMT -    MSB first, 32-bit slots, CPU bus, 0 bit delay */
0x00000000, /* AFSXCTL - burst, single bit frame sync, ext FS */
0x000000c0, /* ACLKXCTL -  Sample on falling CLK, divide by 1, ext CLK */
0x00000000, /* AHCLKXCTL - External HCLK */
0x00000001, /* XTDM -    Slots 0-31 are active */
0x00000000, /* XINTCTL - No interrupts */
0x00000000  /* XCLKCHK - Not used */
};

MCASP_ConfigSrctl mcaspCfgDataSrctl = {
0x0000000d, /* SRCTL0 - Transmit, active high */
0x0000000e, /* SRCTL1 - Receive, active high */
0x00000000, /* SRCTL2 - Inactive */
0x00000000, /* SRCTL3 - Inactive */
0x00000000, /* SRCTL4 - Inactive */
0x00000000, /* SRCTL5 - Inactive */
0x00000000, /* SRCTL6 - Inactive */
0x00000000  /* SRCTL7 - Inactive */
};

MCASP_Config mcaspCfgData = {
&mcaspCfgDataGbl,
&mcaspCfgDataRcv,
&mcaspCfgDataXmt,
&mcaspCfgDataSrctl
};

/*
*  ======== EVMDM642_AIC23_openCodec ========
*  Open the codec and return a codec handle
*/
EVMDM642_AIC23_CodecHandle EVMDM642_AIC23_openCodec(Int16 id, EVMDM642_AIC23_Config *Config, Int16 direction)
{
Uint32 gblctl;

/* Configure the AIC23 */
EVMDM642_AIC23_config(id, Config);

/* Open and configure the McASP */
EVMDM642_AIC23_hMcASP = MCASP_open(MCASP_DEV0, MCASP_OPEN_RESET);
MCASP_config(EVMDM642_AIC23_hMcASP, &mcaspCfgData);

/* Clear transmit and receive status */
MCASP_RSETH(EVMDM642_AIC23_hMcASP, RSTAT, 0xffff);
MCASP_RSETH(EVMDM642_AIC23_hMcASP, XSTAT, 0xffff);

/* Clear GBLCTL */
gblctl = 0;
MCASP_RSETH(EVMDM642_AIC23_hMcASP, GBLCTL, gblctl);

/* Enable transmit/receive serializers */
if ((direction & EVMDM642_AIC23_INPUT) != 0)
      gblctl |= 0x4;
if ((direction & EVMDM642_AIC23_OUTPUT) != 0)
      gblctl |= 0x400;
MCASP_RSETH(EVMDM642_AIC23_hMcASP, GBLCTL, gblctl);

/* Enable transmit/receive state machines */
if ((direction & EVMDM642_AIC23_INPUT) != 0)
      gblctl |= 0x8;
if ((direction & EVMDM642_AIC23_OUTPUT) != 0)
{
      MCASP_RSETH(EVMDM642_AIC23_hMcASP, XBUF0, 0);
      gblctl |= 0x800;
}
MCASP_RSETH(EVMDM642_AIC23_hMcASP, GBLCTL, gblctl);

return TRUE;
}

evmdm642_aic23_read.c

/*
*  Copyright 2003 by Spectrum Digital Incorporated.
*  All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
*  ======== evmdm642_aic23_read16.c ========
*  EVMDM642_AIC23_read() implementation
*/

#include
#include

/*
*  ======== EVMDM642_AIC23_read ========
*  Read a 32-bit value from the codec
*/
Int16 EVMDM642_AIC23_read(EVMDM642_AIC23_CodecHandle hCodec, Uint32 *val)
{
/* If McASP doesn't have new data available, return false */
if ((MCASP_RGETH(EVMDM642_AIC23_hMcASP, SRCTL1) & 0x20) == 0) {
      return (FALSE);
}

/* Read the data */
*val = MCASP_RGETH(EVMDM642_AIC23_hMcASP, XBUF1);

return (TRUE);
}

evmdm642_aic23_registers.c

/*
*  Copyright 2003 by Spectrum Digital Incorporated.
*  All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
*  ======== evmdm642_aic23_registers.c ========
*  EVMDM642_AIC23_rset() and EVMDM642_AIC23_rget() implementation
*/

#include
#include

#include
#include

/* Internal codec state used to simulate read/write functionality */
static EVMDM642_AIC23_Config codecstate = EVMDM642_AIC23_DEFAULTCONFIG;

static I2C_Config aic23XmtCfg = {
0x0000007f, /* I2COAR - Not used if master */
0x00000000, /* I2CIER - Disable interrupts, use polling */
0x0000001b, /* I2CCLKL - Low period for 100KHz operation */
0x0000001b, /* I2CCLKH - High period for 100KHz operation */
0x00000002, /* I2CCNT - Data words per transmission */
0x0000001a, /* I2CSAR - Slave address */
0x00004ea0, /* I2CMDR - Mode */
0x00000019  /* I2CPSC - Prescale 300MHz to 12MHz */
};

/*
*  ======== EVMDM642_AIC23_rset ========
*  Set codec register regnum to value regval
*/
void EVMDM642_AIC23_rset(EVMDM642_AIC23_CodecHandle hCodec, Uint16 regnum, Uint16 regval)
{
Uint16 data;
I2C_Config prevI2CCfg;

/* Mask off lower 9 bits */
regval &= 0x1ff;

/* Set transmit data */
data = (regnum << 9) | regval;

/* Wait until bus is free */
while (I2C_bb(EVMDM642_I2C_hI2C));

/* Save old settings */
I2C_getConfig(EVMDM642_I2C_hI2C, &prevI2CCfg);

/* Restore settings for AIC23 */
I2C_config(EVMDM642_I2C_hI2C, &aic23XmtCfg);

/* Submit the MSB for transmit */
I2C_RSETH(EVMDM642_I2C_hI2C, I2CDXR, (data >> 8) & 0xff);

/* Generate start condition, starts transmission */
I2C_start(EVMDM642_I2C_hI2C);

/* Wait until MSB transmit is done */
while(!I2C_xrdy(EVMDM642_I2C_hI2C));

/* Submit the LSB for transmit */
I2C_writeByte(EVMDM642_I2C_hI2C, data & 0xff);

/* Generate stop condition */
I2C_sendStop(EVMDM642_I2C_hI2C);

/* Wait until bus is free */
while (I2C_bb(EVMDM642_I2C_hI2C));

/* Save register value if regnum is in range */
if (regnum < EVMDM642_AIC23_NUMREGS)
      codecstate.regs[regnum] = regval;

/* Short delay for AIC23 to accept command */
EVMDM642_waitusec(20);

/* Reconfigure I2C with old settings */
I2C_config(EVMDM642_I2C_hI2C, &prevI2CCfg);
}

/*
*  ======== EVMDM642_AIC23_rget ========
*  Return value of codec register regnum
*/
Uint16 EVMDM642_AIC23_rget(EVMDM642_AIC23_CodecHandle hCodec, Uint16 regnum)
{
if (regnum < EVMDM642_AIC23_NUMREGS)
      return codecstate.regs[regnum];
else
      return 0;
}

/*
*  ======== EVMDM642_AIC23_config ========
*  Set the default codec register config values
*/
void EVMDM642_AIC23_config(EVMDM642_AIC23_CodecHandle hCodec, EVMDM642_AIC23_Config *Config)
{
int i;

/* Use default parameters if none are given */
if (Config == NULL)
         Config = &codecstate;

/* Reset the codec */
EVMDM642_AIC23_rset(hCodec, 15, 0);

/* Assign each register */
for (i = 0; i < EVMDM642_AIC23_NUMREGS; i++)
{
      if (i != 6)
         EVMDM642_AIC23_rset(hCodec, i, Config -> regs);
}
EVMDM642_AIC23_rset(hCodec, 6, Config -> regs[6]);
}