void TIMER0_BRK_UP_TRG_COM_IRQHandler(void)
{
timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_CMT);
switch(step){
/* next step: step 2 configuration .V-W` breakover---------------------------- */
case 1:
/* channel0 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM1);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_ENABLE);
break;
/* next step: step 3 configuration .U'-V breakover---------------------------- */
case 2:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM1);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_ENABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
break;
/* next step: step 4 configuration .U'-W breakover---------------------------- */
case 3:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM1);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_ENABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
break;
/* next step: step 5 configuration .V'-W breakover---------------------------- */
case 4:
/* channel0 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM1);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_ENABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
break;
/* next step: step 6 configuration .U-V` breakover---------------------------- */
case 5:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM1);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_ENABLE);
/* channel2 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
break;
/* next step: step 1 configuration .U-W` breakover---------------------------- */
case 6:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM1);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_ENABLE);
break;
default:
/* channel0 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
break;
}
// delay_decrement();
}