fpga除法器的一些算法问题

xuhongming

fpga除法器的一些算法问题 [复制链接]

学习fpga有一段时间的朋友们，你们有没有比较好的除法器的设计思想，目前我的思想进局限于移位—>比较—>减法这种思想，希望有好的想法的朋友介绍一下，比如是速度快，或者使用资源少之类的一些算法。目前正在做等精度频率计除法模块，用quartus中自带的除法器时，当输入被除数为28位，除数为16位时，就消耗了780多个逻辑元件了。

chenzhufly

整体思路问题不大，可以实现

xuhongming

本帖最后由 xuhongming 于 2014-3-26 20:32 编辑

谢谢版主的回复，不应该仅仅只追求实现吧，消耗的硬件资源和速度这些都需要考虑的吧，在网上又找到一个新的思路，加减交替，不知版主是否能具体介绍几个算法，研究研究，谢谢了

k331922164

--this is an add-subtraction alternate divider of the original code
--output fraction
--e.g. X=1.1001(-0.5625/-9),Y=0.1011(0.6875/11),Q=1.1101(-0.8125),F=(0.0078125),the MSB is sign bit;
-- X must less than Y;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity serial_divider is
generic (
x_bitwidth : integer := 5; --dividend bit width
y_bitwidth : integer := 5; --divisor bit width
q_bitwidth : integer := 5 --quotient bit width
);
port(
n_rst,clk,en: in std_logic;
X : in std_logic_vector(x_bitwidth-1 downto 0);--input dividend
Y : in std_logic_vector(y_bitwidth-1 downto 0);--input divisor
quotient : out std_logic_vector(q_bitwidth-1 downto 0)
--X,Y,quotient,fraction are original codes
);
end serial_divider;
architecture rtl of serial_divider is
type m_state is(
idle,
clear, --clear all registers
is_ov, --judge whether division overflows;
comput, --comput division
finish --output quotient,fraction,ov flag bit
);
signal cs,ns: m_state;
signal clr,load,comput_en,comput_over,oe : std_logic;
signal is_ov_en : std_logic;
signal reg_x : std_logic_vector(x_bitwidth-2 downto 0);
signal reg_y : std_logic_vector(y_bitwidth-2 downto 0);
signal reg_yc : std_logic_vector(y_bitwidth-1 downto 0);
signal q_MSB : std_logic;
signal bit_cnt : integer range 0 to q_bitwidth-1;
signal remain : std_logic_vector(x_bitwidth-1 downto 0);
signal result_tmp : std_logic_vector(q_bitwidth-1 downto 0);
begin
--three segments FSM
--timing sequence part of FSM
process(clk,n_rst,en)
begin
if(n_rst='0')then
cs<=idle;
elsif(clk'event and clk='1')then
if(en='1')then
cs<=ns;
end if;
end if;
end process;
--combination part of FSM
process(cs,comput_over)
begin
case (cs) is
when idle => ns<=clear;
when clear => ns<=is_ov;
when is_ov => ns<=comput;
when comput => if(comput_over='1')then
ns<=finish;
else
ns<=comput;
end if;
when finish => ns<=idle;
when others => ns<=idle;
end case;
end process;
--register output part of FSM
process(clk)
begin
if(clk'event and clk='1')then
case (ns) is
when idle =>clr<='0';load<='0';comput_en<='0';is_ov_en<='0';oe<='0';
when clear =>clr<='1';load<='1';comput_en<='0';is_ov_en<='0';oe<='0';
when is_ov =>clr<='0';load<='0';comput_en<='0';is_ov_en<='1';oe<='0';
when comput =>clr<='0';load<='0';comput_en<='1';is_ov_en<='0';oe<='0';
when finish =>clr<='0';load<='0';comput_en<='0';is_ov_en<='0';oe<='1';
when others =>clr<='0';load<='0';comput_en<='0';is_ov_en<='0';oe<='0';
end case;
end if;
end process;
--count times of computing
process(clk)
begin
if(clk'event and clk='1')then
if(clr='1')then
bit_cnt <= 0;
elsif(comput_en='1')then
if(bit_cnt=q_bitwidth-1)then
comput_over <= '1';
bit_cnt <= 0;
else
comput_over <= '0';
bit_cnt <= bit_cnt + 1;
end if;
else
comput_over <= '0';
bit_cnt <= 0;
end if;
end if;
end process;
--judge quotient sign bit
process(clk)
begin
if(clk'event and clk='1')then
if(load='1')then
q_MSB <= X(x_bitwidth-1) xor Y(y_bitwidth-1);
reg_x <= X(x_bitwidth-2 downto 0);
reg_y <= Y(y_bitwidth-2 downto 0);
reg_yc <= not ('0' & Y(y_bitwidth-2 downto 0)) + 1;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
if(clr='1')then
remain <= (others=>'0');
result_tmp <= (others=>'0');
elsif(is_ov_en='1' and comput_en='0')then
remain <= reg_x + reg_yc;
elsif(is_ov_en='0' and comput_en='1')then
if(remain(x_bitwidth-1)='1')then
remain <= (remain(x_bitwidth-2 downto 0) & '0') + reg_y;
result_tmp <= result_tmp(q_bitwidth-2 downto 0) & '0';
else
remain <= (remain(x_bitwidth-2 downto 0) & '0') + reg_yc;
result_tmp <= result_tmp(q_bitwidth-2 downto 0) & '1';
end if;
end if;
end if;
end process;
--output quotient,faction,ov flag bit
process(n_rst,clk)
begin
if(n_rst='0')then
quotient <= (others=>'0');
elsif(clk'event and clk='1')then
if(oe='1')then
quotient <= q_MSB & result_tmp(q_bitwidth-1 downto 1);
end if;
end if;
end process;
end rtl;

复制代码

k331922164

上面是我写的原码一位除法，是加减交替除法

xuhongming

k331922164 发表于 2014-3-27 10:31
上面是我写的原码一位除法，是加减交替除法

谢谢回复，但目前是在用verilog学习fpga，VHDL还不太懂，但还是谢谢你的热心帮助

fpga除法器的一些算法问题 [复制链接]

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