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一粒金砂(初级)

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verilog warning 请求帮助 [复制链接]

Warning: Using design file convert.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
     Info: Found entity 1: convert
Warning (14130): Reduced register "convert:uc|out4[11]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "convert:uc|out4[10]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "convert:uc|out4[9]" with stuck data_in port to stuck value GND

Warning: Synthesized away the following node(s):
     Warning: Synthesized away the following DSP element node(s):
          Warning (14320): Synthesized away node "convert:uc|mult8x8:m32|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|mac_mult1"
          Warning (14320): Synthesized away node "convert:uc|mult8x8:m32|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|result[0]"
          Warning (14320): Synthesized away node "convert:uc|mult8x8:m22|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|mac_mult1"

Warning: Synthesized away the following node(s):
     Warning: Synthesized away the following DSP element node(s):
          Warning (14320): Synthesized away node "convert:uc|mult8x8:m32|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|mac_mult1"
          Warning (14320): Synthesized away node "convert:uc|mult8x8:m32|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|result[0]"
          Warning (14320): Synthesized away node "convert:uc|mult8x8:m22|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|mac_mult1"

Warning: Output pins are stuck at VCC or GND
     Warning (13410): Pin "oRED[0]" stuck at GND
     Warning (13410): Pin "oRED[1]" stuck at GND
     Warning (13410): Pin "oRED[2]" stuck at GND

Warning: Design contains 36 input pin(s) that do not drive logic
     Warning (15610): No output dependent on input pin "iRED[0]"
     Warning (15610): No output dependent on input pin "iRED[1]"
     Warning (15610): No output dependent on input pin "iRED[2]"


Warning: No exact pin location assignment(s) for 76 pins of 76 total pins
     Info: Pin iRED[0] not assigned to an exact location on the device
     Info: Pin iRED[1] not assigned to an exact location on the device
     Info: Pin iRED[2] not assigned to an exact location on the device

Warning: Found 37 output pins without output pin load capacitance assignment
     Info: Pin "oDVAL" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "oRED[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "oRED[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "oRED[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis

Warning: Following 36 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
     Info: Pin oRED[0] has GND driving its datain port
     Info: Pin oRED[1] has GND driving its datain port
     Info: Pin oRED[2] has GND driving its datain port
     Info: Pin oRED[3] has GND driving its datain port

Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Found pins functioning as undefined clocks and/or memory enables
     Info: Assuming node "iCLK" is an undefined clock

特别是
1.Reduced register "convert:uc|out4[11]" with stuck data_in port to stuck value GND
2.Warning (13410): Pin "oRED[0]" stuck at GND
3.Warning (15610): No output dependent on input pin "iRED[1]"
希望各位高手帮助一下
此帖出自FPGA/CPLD论坛

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路过~  详情 回复 发表于 2010-3-1 12:08
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裸片初长成(初级)

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1.Reduced register "convert:uc|out4[11]" with stuck data_in port to stuck value GND 意思是convert:uc|out4[11]因为输入端口而固定为GND值不变,所以编绎器去掉这个寄存器。
2Warning (13410): Pin "oRED[0]" stuck at GND 指输入或输出引脚在程序中的逻辑值没有变化一直是GND(0);这大多是因为程序错误(有可能是程序员的本来目的)
3Warning (15610): No output dependent on input pin "iRED[1]" 是指程序中没有任何变量的值根据输入引脚iRED[1]而变化。即该输入端口也可有可无了,这通常是程序错误引起的。
此帖出自FPGA/CPLD论坛
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一粒金砂(中级)

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路过~
此帖出自FPGA/CPLD论坛
 
 
 

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