library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choose is
port(clk: in std_logic;
a: in integer range 0 to 100;
b: in integer range 0 to 100;
c: in integer range 0 to 100;
d: in integer range 0 to 100;
max: in integer range 0 to 100;
min: in integer range 0 to 100);
end entity choose;
architecture behave of choose is
begin
u1: process(clk,a,b)
variable t1: integer range 0 to 100;
variable m1: integer range 0 to 100;
begin
if(a>b)then t1
详情回复
发表于 2010-1-2 22:07
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choose is
port(clk: in std_logic;
a: in integer range 0 to 100;
b: in integer range 0 to 100;
c: in integer range 0 to 100;
d: in integer range 0 to 100;
max: in integer range 0 to 100;
min: in integer range 0 to 100);
end entity choose;
architecture behave of choose is
begin
u1: process(clk,a,b)
variable t1: integer range 0 to 100;
variable m1: integer range 0 to 100;
begin
if(a>b)then t1<=a;m1<=b;
else t1<=b;m1<=a;
end if;
end process;
u2: process(clk,t1,m1,c)
variable t2: integer range 0 to 100;
variable m2: integer range 0 to 100;
begin
if(t1
elsif(m1>c) then m2<=c;t2<=t1;
end if;
end process;
u3: process(clk,t2,m2)
begin
if(t2
elsif(m2>d) then min<=d;max<=t2;
end if;
end process;
end architecture behave;