状态机显示被综合掉

oenandone2017

本人新手一枚，在写状态机的时候综合时出现了问题，求助各位大神，代码如下


LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY control IS
  PORT
  (
     clk : IN STD_LOGIC; -- Standard ports
     reset : IN STD_LOGIC; --Recive a signal from the rest key
     start_pause : IN STD_LOGIC;  --Recive a signal from the start or pause key
     zero : IN STD_LOGIC;  --Recive the zero signal from the counter
     cnt_en : OUT STD_LOGIC; --Give out a singal to run the counter
     cnt_reset : OUT STD_LOGIC; --Give out a singal to reset the counter
     alarm_en : OUT STD_LOGIC --Give out a signal to the alarm clock
   );
END ;
ARCHITECTURE bhv of control IS
TYPE states IS (s0, s1, s2) ;
  SIGNAL cs, next_state: states :=s0 ;
BEGIN
REG: PROCESS (clk,reset) BEGIN
         IF reset='0'
           THEN cs <= s0;
                cnt_reset <='1';--?
         ELSIF  clk'EVENT AND clk='1'
           THEN cs <= next_state;
                cnt_reset <='0'; --?
         END IF;
END PROCESS REG;


COM: PROCESS(cs, start_pause)  BEGIN
         CASE cs IS
           WHEN s0 => cnt_en<='0';
             IF (start_pause='1') AND (zero <='0' )
               THEN next_state <= s1;
                 ELSE  next_state <= s0;
            END IF;
           WHEN s1 => cnt_en<='1';
             IF zero='1'
               THEN next_state <= s0;
             ELSIF (start_pause='1')  
               THEN next_state <= s2;
             ELSE  next_state <= s1;
             END IF;
           WHEN s2 => cnt_en<='0';
             IF (start_pause='1')  
               THEN next_state <= s1;
                 ELSE  next_state <= s2;
             END IF;
           WHEN OTHERS => next_state <= s0;
         END CASE;
END PROCESS COM;
alarm_en <=zero;
END bhv;

oenandone2017

图片

oenandone2017

求助

dl121

你这个状态机会锁死在S1和S2状态里的