请问怎么消除锁存器？

destiny_zm

请问怎么消除锁存器？ [复制链接]

是带7位数码管的模100计数器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
       port(clk,rst:in std_logic;
                      digit1,digit2:out std_logic_vector(6 downto 0));
end top;

architecture Behavioral of top is
begin
     process(clk,rst)
           variable temp1,temp2:integer range 0 to 10;
          begin
     if(rst='1')then
          temp1:=0;
          temp2:=0;
     elsif(clk'event and clk='1')then
          temp1:=temp1+1;
          if(temp1=10)then
          temp1:=0;
          temp2:=temp2+1;
          if(temp2=10)then
          temp2:=0;
     end if;
          end if;
          end if;

   case temp1 is
        when 0 => digit1 <= "1111110";
        when 1 => digit1 <= "0110000";
        when 2 => digit1 <= "1101101";
        when 3 => digit1 <= "1111001";
        when 4 => digit1 <= "0110011";
        when 5 => digit1 <= "1011011";
        when 6 => digit1 <= "1011111";
        when 7 => digit1 <= "1110000";
        when 8 => digit1 <= "1111111";
        when 9 => digit1 <= "1111011";
        when others => null;
        end case;
       
        case temp2 is
        when 0 => digit2 <= "1111110";
        when 1 => digit2 <= "0110000";
        when 2 => digit2 <= "1101101";
        when 3 => digit2 <= "1111001";
        when 4 => digit2 <= "0110011";
        when 5 => digit2 <= "1011011";
        when 6 => digit2 <= "1011111";
        when 7 => digit2 <= "1110000";
        when 8 => digit2 <= "1111111";
        when 9 => digit2 <= "1111011";
        when others => null;
        end case;
end process;
end Behavioral;
总是有如下的警告
WARNING:HDLCompiler:1369 - "C:\Users\zm\counter\top.vhd" Line 11: Possible infinite loop; process does not have a wait statement
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

gs001588

1. library IEEE;
   
2. use IEEE.STD_LOGIC_1164.ALL;
   
3. 
   
4. entity top is
   
5.         port(
   
6.        clk,rst:in std_logic;
   
7.        digit1,digit2:out std_logic_vector(6 downto 0)
   
8.     );
   
9. end top;
   
10. 
    
11. architecture Behavioral of top is
    
12. begin
    
13. 
    
14. process(clk,rst)
    
15. variable temp1,temp2:integer range 0 to 10;
    
16. begin
    
17.         if(rst='1')then
    
18.                 temp1:=0;
    
19.                 temp2:=0;
    
20.         elsif(clk'event and clk='1')then
    
21.                 temp1:=temp1+1;
    
22.                 if(temp1=10)then
    
23.                         temp1:=0;
    
24.                         temp2:=temp2+1;
    
25.                         if(temp2=10)then
    
26.                                 temp2:=0;
    
27.                         end if;
    
28.                 end if;
    
29.         end if;
    
30. 
    
31.         if(clk'event and clk='1')then
    
32.                 case temp1 is
    
33.                         when 0 => digit1 <= "1111110";
    
34.                         when 1 => digit1 <= "0110000";
    
35.                         when 2 => digit1 <= "1101101";
    
36.                         when 3 => digit1 <= "1111001";
    
37.                         when 4 => digit1 <= "0110011";
    
38.                         when 5 => digit1 <= "1011011";
    
39.                         when 6 => digit1 <= "1011111";
    
40.                         when 7 => digit1 <= "1110000";
    
41.                         when 8 => digit1 <= "1111111";
    
42.                         when 9 => digit1 <= "1111011";
    
43.                         when others => null;
    
44.                 end case;
    
45.         end if;
    
46.        
    
47.         if(clk'event and clk='1')then
    
48.                 case temp2 is
    
49.                         when 0 => digit2 <= "1111110";
    
50.                         when 1 => digit2 <= "0110000";
    
51.                         when 2 => digit2 <= "1101101";
    
52.                         when 3 => digit2 <= "1111001";
    
53.                         when 4 => digit2 <= "0110011";
    
54.                         when 5 => digit2 <= "1011011";
    
55.                         when 6 => digit2 <= "1011111";
    
56.                         when 7 => digit2 <= "1110000";
    
57.                         when 8 => digit2 <= "1111111";
    
58.                         when 9 => digit2 <= "1111011";
    
59.                         when others => null;
    
60.                 end case;
    
61.         end if;
    
62. end process;
    
63. 
    
64. end Behavioral;

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destiny_zm