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你研究研究下面的官方例程吧,注意时钟设置:
- //******************************************************************************
- // MSP430x41x2 Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK, LPM3
- //
- // Description: Echo a received character, RX ISR used. Normal mode is LPM3.
- // Automatic clock activation for SMCLK through the USCI is demonstrated.
- // USCI_A0 RX interrupt triggers TX Echo.
- // Baud rate divider with 1048576hz = 1048576/115200 = ~9.1 (009h|01h)
- // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
- // //* An external watch crystal between XIN & XOUT is required for ACLK *//
- //
- // MSP430x41x2
- // -----------------
- // /|\| XIN|-
- // | | | 32kHz
- // --|RST XOUT|-
- // | |
- // | P6.6/UCA0TXD|------------>
- // | | 115200 - 8N1
- // | P6.5/UCA0RXD|<------------
- //
- //
- // P. Thanigai
- // Texas Instruments Inc.
- // January 2009
- // Built with CCE Version: 3.1 and IAR Embedded Workbench Version: 4.11
- //******************************************************************************
- #include <msp430x41x2.h>
- void main(void)
- {
- volatile unsigned int i;
- WDTCTL = WDTPW+WDTHOLD; // Stop WDT
- FLL_CTL0 |= XCAP14PF; // Configure load caps
- do
- {
- IFG1 &= ~OFIFG; // Clear OSCFault flag
- for (i = 0x47FF; i > 0; i--); // Time for flag to set
- }
- while ((IFG1 & OFIFG)); // OSCFault flag still set?
- P6SEL |= BIT5+BIT6; // P6.5,6 = USCI_A0 RXD/TXD
- UCA0CTL1 |= UCSSEL_2; // SMCLK
- UCA0BR0 = 0x09; // 1MHz 115200
- UCA0BR1 = 0x00; // 1MHz 115200
- UCA0MCTL = 0x02; // Modulation
- UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
- IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt
- __bis_SR_register(LPM3_bits + GIE); // Enter LPM3, interrupts enabled
- }
- // Echo back RXed character, confirm TX buffer is ready first
- #pragma vector=USCIAB0RX_VECTOR
- __interrupt void USCI0RX_ISR(void)
- {
- while (!(IFG2&UCA0TXIFG)); // USCI_A0 TX buffer ready?
- UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
- }
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