F28335的ECAN初始化

elvike

F28335的ECAN初始化 [复制链接]

can初始化总是掉在下面这个循环里面。求助！


do

        {

                ECanaShadow.CANES.all = ECanaRegs.CANES.all;

        } while(ECanaShadow.CANES.bit.CCE != 0 );                 // Wait for CCE bit to be  cleared..






初始化程序采用的ti的例程里面的初始化程序，里面有2个这样的等待语句，过了第一个，在第二个里面等死。


        SysCtrlRegs.PCLKCR0.bit.ECANAENCLK= 1;    // eCAN-A

        SysCtrlRegs.PCLKCR0.bit.ECANBENCLK= 1;    // eCAN-B


can的时钟已经使能了。







导入ti的官方ECAN例程，又没有问题。求助！！！！

elvike

问题找到了。
void InitECana(void)                // Initialize eCAN-A module
{
        /* Create a shadow register structure for the CAN control registers. This is
        needed, since only 32-bit access is allowed to these registers. 16-bit access
        to these registers could potentially corrupt the register contents or return
        false data. This is especially true while writing to/reading from a bit
        (or group of bits) among bits 16 - 31 */

        struct ECAN_REGS ECanaShadow;

       
        // Enables access to protected bits
        UNPROTECT_REGS();       

        /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

        ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
        ECanaShadow.CANTIOC.bit.TXFUNC = 1;
        ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

        ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
        ECanaShadow.CANRIOC.bit.RXFUNC = 1;
        ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

        /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
                                                                        // HECC mode also enables time-stamping feature

        ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
        ECanaShadow.CANMC.bit.SCB = 1;
        ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;



        /* Initialize all bits of 'Master Control Field' to zero */
        // Some bits of MSGCTRL register come up in an unknown state. For proper operation,
        // all bits (including reserved bits) of MSGCTRL must be initialized to zero

        ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
        ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;



        // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
        //        as a matter of precaution.
        ECanaRegs.CANTA.all        = 0xFFFFFFFF;        /* Clear all TAn bits */

        ECanaRegs.CANRMP.all = 0xFFFFFFFF;        /* Clear all RMPn bits */

        ECanaRegs.CANGIF0.all = 0xFFFFFFFF;        /* Clear all interrupt flag bits */
        ECanaRegs.CANGIF1.all = 0xFFFFFFFF;


        /* Configure bit timing parameters for eCANA*/
        ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
        ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
        ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
        ECanaShadow.CANES.all = ECanaRegs.CANES.all;

        //
        do
        {
            ECanaShadow.CANES.all = ECanaRegs.CANES.all;
        } while(ECanaShadow.CANES.bit.CCE != 1 );                  // Wait for CCE bit to be set..

        ECanaShadow.CANBTC.all = 0;



#if (CPU_FRQ_150MHZ)                       
        // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
        /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
        See Note at End of File */
        ECanaShadow.CANBTC.bit.BRPREG = 4;
        ECanaShadow.CANBTC.bit.TSEG2REG = 2;
        ECanaShadow.CANBTC.bit.TSEG1REG = 10;
#endif

#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
        /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
        See Note at End of File */
        ECanaShadow.CANBTC.bit.BRPREG = 4;
        ECanaShadow.CANBTC.bit.TSEG2REG = 1;
        ECanaShadow.CANBTC.bit.TSEG1REG = 6;
#endif

        //
        ECanaShadow.CANBTC.bit.SAM = 1;
        ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

        ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
        ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
        ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

        ECanaShadow.CANES.all = ECanaRegs.CANES.all;

        do
        {
                ECanaShadow.CANES.all = ECanaRegs.CANES.all;
        } while(ECanaShadow.CANES.bit.CCE != 0 );                 // Wait for CCE bit to be  cleared..

        /* Disable all Mailboxes  */
        ECanaRegs.CANME.all = 0;                // Required before writing the MSGIDs

        PROTECT_REGS();
}


问题在于下面这段代码中的CPU_FRQ_150MHZ虽然在其他头文件里面定义了为1，但是没有把这个头文件包含到这个源文件里面。#include "DSP2833x_Platform.h"。
#if (CPU_FRQ_150MHZ)                       
        // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
        /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
        See Note at End of File */
        ECanaShadow.CANBTC.bit.BRPREG = 4;
        ECanaShadow.CANBTC.bit.TSEG2REG = 2;
        ECanaShadow.CANBTC.bit.TSEG1REG = 10;
#endif

小涩涩asd

谢谢楼主分享

kata

检查CANTX和CANRX引脚，实在不行把这两个引脚都悬浮起来试试

elvike

kata 发表于 2015-9-7 20:46
检查CANTX和CANRX引脚，实在不行把这两个引脚都悬浮起来试试

已解决，谢谢