求大神助攻，OpenCL编译出现internal compiler error

1696811157

求大神助攻，OpenCL编译出现internal compiler error [复制链接]

 这是一个官网下载的FFT例子，编译两小时后下一行就会出现internal compiler error。。。。。DE1-soc OpenCL DSP自带的其它例子可以编译，这是什么情况呢

1696811157

zhaoyongke

Show me the code please

1696811157

zhaoyongke 发表于 2015-6-2 10:33
Show me the code please

https://www.altera.com.cn/suppor ... /opencl/opencl.html
在这个地址下载的FFT例子，用到软件版本是14.0，开发板用DE1。Thank you！

1696811157

zhaoyongke 发表于 2015-6-2 10:33
Show me the code please

https://www.altera.com.cn/suppor ... /opencl/opencl.html
其中FFT1d的例子，所用软件是14.0.谢谢

zhaoyongke

1696811157 发表于 2015-6-2 15:24
https://www.altera.com.cn/support/support-resources/design-examples/design-software/opencl/opencl.html
其中FFT1d的例子，所用软件是14.0.谢谢

正在编译，等等看会不会出现你说的情形

zhaoyongke

找到原因了，资源用爆了，建议用其他板子试试。

1. ======================================================================================================================
   
2. |                                          *** Optimization Report ***                                               |
   
3. | Warning: Compile with "-g" to get line number and variable name information                                        |
   
4. ======================================================================================================================
   
5. | Kernel: fft1d                                                                                            | Ln.Col  |
   
6. ======================================================================================================================
   
7. | Loop for.body                                                                                            |         |
   
8. |     Pipelined execution inferred.                                                                        |         |
   
9. ======================================================================================================================
   
10. 
    
11. 
    
12. +--------------------------------------------------------------------+
    
13. ; Estimated Resource Usage Summary                                   ;
    
14. +----------------------------------------+---------------------------+
    
15. ; Resource                               + Usage                     ;
    
16. +----------------------------------------+---------------------------+
    
17. ; Logic utilization                      ;  144%                     ;
    
18. ; Dedicated logic registers              ;   64%                     ;
    
19. ; Memory blocks                          ;   32%                     ;
    
20. ; DSP blocks                             ;  107%                     ;
    
21. +----------------------------------------+---------------------------;
    
22. System name: fft1d
    
23. 
    
24. Placing kernel fft1d at address 0x0
    
25. 2015.06.03.09:21:34 Info: Doing: <b>qsys-script --script=system.tcl --Xmx512M --XX:+UseSerialGC --system-file=system.qsys</b>
    
26. 2015.06.03.09:22:34 Info: set_validation_property AUTOMATIC_VALIDATION false
    
27. 2015.06.03.09:22:34 Info: add_instance fft1d_system fft1d_system
    
28. 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_clk fft1d_system.clock_reset
    
29. 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_clk2x fft1d_system.clock_reset2x
    
30. 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_reset fft1d_system.clock_reset_reset
    
31. 2015.06.03.09:22:34 Info: add_connection fft1d_system.avm_memgmem0_port_0_0_rw acl_iface.kernel_mem0
    
32. 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_irq fft1d_system.kernel_irq
    
33. 2015.06.03.09:22:34 Info: add_instance cra_root cra_ring_root
    
34. 2015.06.03.09:22:35 Info: set_instance_parameter_value cra_root DATA_W 64
    
35. 2015.06.03.09:22:35 Info: set_instance_parameter_value cra_root ADDR_W 4
    
36. 2015.06.03.09:22:35 Info: set_instance_parameter_value cra_root ID_W 0
    
37. 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_clk cra_root.clock
    
38. 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_reset cra_root.reset
    
39. 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_cra cra_root.cra_slave
    
40. 2015.06.03.09:22:35 Info: set_connection_parameter_value acl_iface.kernel_cra/cra_root.cra_slave baseAddress 0x0
    
41. 2015.06.03.09:22:35 Info: add_instance avs_fft1d_cra_cra_ring cra_ring_node
    
42. 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring DATA_W 64
    
43. 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring RING_ADDR_W 4
    
44. 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring CRA_ADDR_W 4
    
45. 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring ID_W 0
    
46. 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring ID 0
    
47. 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_clk avs_fft1d_cra_cra_ring.clock
    
48. 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_reset avs_fft1d_cra_cra_ring.reset
    
49. 2015.06.03.09:22:35 Info: add_connection cra_root.ring_out avs_fft1d_cra_cra_ring.ring_in
    
50. 2015.06.03.09:22:35 Info: add_connection avs_fft1d_cra_cra_ring.cra_master fft1d_system.avs_fft1d_cra
    
51. 2015.06.03.09:22:35 Info: set_connection_parameter_value avs_fft1d_cra_cra_ring.cra_master/fft1d_system.avs_fft1d_cra baseAddress 0x0
    
52. 2015.06.03.09:22:35 Info: add_connection avs_fft1d_cra_cra_ring.ring_out cra_root.ring_in
    
53. 2015.06.03.09:22:35 Info: save_system
    
54. 2015.06.03.09:22:38 Progress: Loading fft1d/system.qsys
    
55. 2015.06.03.09:22:38 Progress: Reading input file
    
56. 2015.06.03.09:22:39 Progress: Adding ext_clk_50 [clock_source 14.0]
    
57. 2015.06.03.09:22:39 Progress: Parameterizing module ext_clk_50
    
58. 2015.06.03.09:22:39 Progress: Adding acl_iface [acl_iface_system 1.0]
    
59. 2015.06.03.09:23:10 Progress: Parameterizing module acl_iface
    
60. 2015.06.03.09:23:10 Progress: Adding fft1d_system [fft1d_system 1.0]
    
61. 2015.06.03.09:23:10 Progress: Parameterizing module fft1d_system
    
62. 2015.06.03.09:23:10 Progress: Adding cra_root [cra_ring_root 1.0]
    
63. 2015.06.03.09:23:10 Progress: Parameterizing module cra_root
    
64. 2015.06.03.09:23:10 Progress: Adding avs_fft1d_cra_cra_ring [cra_ring_node 1.0]
    
65. 2015.06.03.09:23:10 Progress: Parameterizing module avs_fft1d_cra_cra_ring
    
66. 2015.06.03.09:23:10 Progress: Building connections
    
67. 2015.06.03.09:23:10 Progress: Parameterizing connections
    
68. 2015.06.03.09:23:10 Progress: Validating
    
69. 2015.06.03.09:23:12 Progress: Done reading input file
    
70. 2015.06.03.09:23:20 Info: system.acl_iface.acl_iface: There are recommended upgrades for: pll
    
71. 2015.06.03.09:23:20 Info: system.acl_iface.acl_kernel_clk.acl_kernel_clk: There are recommended upgrades for: kernel_pll
    
72. 2015.06.03.09:23:20 Info: system.acl_iface.acl_kernel_clk.kernel_pll: The legal reference clock frequency is 50.0 MHz..800.0 MHz
    
73. 2015.06.03.09:23:20 Info: system.acl_iface.acl_kernel_clk.kernel_pll: Able to implement PLL with user settings
    
74. 2015.06.03.09:23:20 Warning: system.acl_iface.acl_kernel_clk.acl_pll_reconfig: set_interface_assignment: Interface "mgmt_waitrequest" does not exist
    
75. 2015.06.03.09:23:20 Warning: system.acl_iface.acl_kernel_clk.global_routing_kernel_clk.global_clk/kernel_clk.clk_in: kernel_clk.clk_in requires 100000000Hz, but source has frequency of 0Hz
    
76. 2015.06.03.09:23:20 Warning: system.acl_iface.hps: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
    
77. 2015.06.03.09:23:20 Warning: system.acl_iface.hps: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
    
78. 2015.06.03.09:23:20 Info: system.acl_iface.pll: The legal reference clock frequency is 5.0 MHz..800.0 MHz
    
79. 2015.06.03.09:23:20 Info: system.acl_iface.pll: Able to implement PLL with user settings
    
80. 2015.06.03.09:23:20 Warning: system.acl_iface: acl_iface.acl_kernel_clk_kernel_pll_locked must be exported, or connected to a matching conduit.
    
81. 2015.06.03.09:23:20 Warning: system.acl_iface: acl_iface.acl_internal_memorg_kernel must be exported, or connected to a matching conduit.
    
82. 2015.06.03.09:23:20 Warning: system.acl_iface: acl_iface.kernel_interface_acl_bsp_memorg_host must be exported, or connected to a matching conduit.
    
83. 2015.06.03.09:23:20 Info: system: Generating system "system" for QUARTUS_SYNTH
    
84. 2015.06.03.09:23:27 Info: Interconnect is inserted between master acl_iface.kernel_cra and slave cra_root.cra_slave because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
    
85. 2015.06.03.09:23:27 Info: Interconnect is inserted between master acl_iface.kernel_cra and slave cra_root.cra_slave because the master has address signal 30 bit wide, but the slave is 4 bit wide.
    
86. 2015.06.03.09:23:27 Info: Interconnect is inserted between master acl_iface.kernel_cra and slave cra_root.cra_slave because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
    
87. 2015.06.03.09:23:40 Info: Interconnect is inserted between master clock_cross_kernel_mem1.m0 and slave address_span_extender_kernel.windowed_slave because the master has address signal 30 bit wide, but the slave is 25 bit wide.
    
88. 2015.06.03.09:23:40 Info: Interconnect is inserted between master clock_cross_kernel_mem1.m0 and slave address_span_extender_kernel.windowed_slave because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
    
89. 2015.06.03.09:23:40 Info: Interconnect is inserted between master address_span_extender_kernel.expanded_master and slave hps.f2h_sdram0_data because the master has address signal 32 bit wide, but the slave is 27 bit wide.
    
90. 2015.06.03.09:23:40 Info: Interconnect is inserted between master address_span_extender_kernel.expanded_master and slave hps.f2h_sdram0_data because the master has burstcount signal 5 bit wide, but the slave is 8 bit wide.
    
91. 2015.06.03.09:23:41 Warning: hps.f2h_irq0: Cannot connect clock for irq_mapper.sender
    
92. 2015.06.03.09:23:41 Warning: hps.f2h_irq0: Cannot connect reset for irq_mapper.sender
    
93. 2015.06.03.09:23:41 Warning: hps.f2h_irq1: Cannot connect clock for irq_mapper_001.sender
    
94. 2015.06.03.09:23:41 Warning: hps.f2h_irq1: Cannot connect reset for irq_mapper_001.sender
    
95. 2015.06.03.09:23:48 Info: acl_iface: "system" instantiated acl_iface_system "acl_iface"
    
96. 2015.06.03.09:23:48 Info: fft1d_system: "system" instantiated fft1d_system "fft1d_system"
    
97. 2015.06.03.09:23:49 Info: cra_root: "system" instantiated cra_ring_root "cra_root"
    
98. 2015.06.03.09:23:49 Info: avs_fft1d_cra_cra_ring: "system" instantiated cra_ring_node "avs_fft1d_cra_cra_ring"
    
99. 2015.06.03.09:23:49 Info: mm_interconnect_0: "system" instantiated altera_mm_interconnect "mm_interconnect_0"
    
100. 2015.06.03.09:23:50 Info: mm_interconnect_1: "system" instantiated altera_mm_interconnect "mm_interconnect_1"
     
101. 2015.06.03.09:23:50 Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper"
     
102. 2015.06.03.09:23:51 Info: Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0
     
103. 2015.06.03.09:23:51 Info: Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2
     
104. 2015.06.03.09:23:53 Info: acl_kernel_clk: "acl_iface" instantiated acl_kernel_clk "acl_kernel_clk"
     
105. 2015.06.03.09:23:53 Info: clock_cross_kernel_mem1: "acl_iface" instantiated altera_avalon_mm_clock_crossing_bridge "clock_cross_kernel_mem1"
     
106. 2015.06.03.09:23:53 Info: version_id: "acl_iface" instantiated version_id "version_id"
     
107. 2015.06.03.09:23:53 Info: hps: "Running  for module: hps"
     
108. 2015.06.03.09:23:54 Warning: hps: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
     
109. 2015.06.03.09:23:54 Warning: hps: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
     
110. 2015.06.03.09:23:56 Info: hps: "acl_iface" instantiated altera_hps "hps"
     
111. 2015.06.03.09:23:56 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because the master has readdata signal 32 bit wide, but the slave is 64 bit wide.
     
112. 2015.06.03.09:23:56 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because the master has writedata signal 32 bit wide, but the slave is 64 bit wide.
     
113. 2015.06.03.09:23:56 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because the master has byteenable signal 4 bit wide, but the slave is 8 bit wide.
     
114. 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
     
115. 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between cmd_demux.src1 and cmd_mux_001.sink0
     
116. 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
     
117. 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between rsp_demux_001.src0 and rsp_mux.sink1
     
118. 2015.06.03.09:23:58 Warning: irq_ena_0.my_irq_in: Cannot connect clock for irq_mapper.sender
     
119. 2015.06.03.09:23:58 Warning: irq_ena_0.my_irq_in: Cannot connect reset for irq_mapper.sender
     
120. 2015.06.03.09:24:00 Info: acl_kernel_interface: "acl_iface" instantiated acl_kernel_interface "acl_kernel_interface"
     
121. 2015.06.03.09:24:00 Info: pll: "acl_iface" instantiated altera_pll "pll"
     
122. 2015.06.03.09:24:00 Info: address_span_extender_kernel: "acl_iface" instantiated altera_address_span_extender "address_span_extender_kernel"
     
123. 2015.06.03.09:24:01 Info: mm_interconnect_0: "acl_iface" instantiated altera_mm_interconnect "mm_interconnect_0"
     
124. 2015.06.03.09:24:01 Info: mm_interconnect_1: "acl_iface" instantiated altera_mm_interconnect "mm_interconnect_1"
     
125. 2015.06.03.09:24:02 Info: mm_interconnect_2: "acl_iface" instantiated altera_mm_interconnect "mm_interconnect_2"
     
126. 2015.06.03.09:24:02 Info: irq_mapper: "acl_iface" instantiated altera_irq_mapper "irq_mapper"
     
127. 2015.06.03.09:24:02 Info: irq_mapper_001: "acl_iface" instantiated altera_irq_mapper "irq_mapper_001"
     
128. 2015.06.03.09:24:02 Info: rst_controller: "acl_iface" instantiated altera_reset_controller "rst_controller"
     
129. 2015.06.03.09:24:02 Info: fft1d_system_avm_memgmem0_port_0_0_rw_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "fft1d_system_avm_memgmem0_port_0_0_rw_translator"
     
130. 2015.06.03.09:24:02 Info: acl_iface_kernel_mem0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "acl_iface_kernel_mem0_translator"
     
131. 2015.06.03.09:24:02 Info: kernel_pll: "acl_kernel_clk" instantiated altera_pll "kernel_pll"
     
132. 2015.06.03.09:24:10 Info: pll_reconfig_0: "acl_kernel_clk" instantiated acl_pll_reconfig "pll_reconfig_0"
     
133. 2015.06.03.09:24:10 Info: pll_rom: Starting RTL generation for module 'system_acl_iface_acl_kernel_clk_pll_rom'
     
134. 2015.06.03.09:24:10 Info: pll_rom:   Generation command is [exec G:/altera/quartus/bin64/perl/bin/perl.exe -I G:/altera/quartus/bin64/perl/lib -I G:/altera/quartus/sopc_builder/bin/europa -I G:/altera/quartus/sopc_builder/bin/perl_lib -I G:/altera/quartus/sopc_builder/bin -I G:/altera/quartus/../ip/altera/sopc_builder_ip/common -I G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=system_acl_iface_acl_kernel_clk_pll_rom --dir=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0015_pll_rom_gen/ --quartus_dir=G:/altera/quartus --verilog --config=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0015_pll_rom_gen//system_acl_iface_acl_kernel_clk_pll_rom_component_configuration.pl  --do_build_sim=0  ]
     
135. 2015.06.03.09:24:12 Info: pll_rom: Done RTL generation for module 'system_acl_iface_acl_kernel_clk_pll_rom'
     
136. 2015.06.03.09:24:12 Info: pll_rom: "acl_kernel_clk" instantiated altera_avalon_onchip_memory2 "pll_rom"
     
137. 2015.06.03.09:24:12 Info: counter: "acl_kernel_clk" instantiated timer "counter"
     
138. 2015.06.03.09:24:12 Info: global_routing_kernel_clk: "acl_kernel_clk" instantiated global_routing_clk "global_routing_kernel_clk"
     
139. 2015.06.03.09:24:12 Info: ctrl: "acl_kernel_clk" instantiated altera_avalon_mm_bridge "ctrl"
     
140. 2015.06.03.09:24:12 Info: pll_sw_reset: "acl_kernel_clk" instantiated sw_reset "pll_sw_reset"
     
141. 2015.06.03.09:24:12 Info: pll_lock_avs_0: "acl_kernel_clk" instantiated pll_lock_avs "pll_lock_avs_0"
     
142. 2015.06.03.09:24:13 Info: mm_interconnect_0: "acl_kernel_clk" instantiated altera_mm_interconnect "mm_interconnect_0"
     
143. 2015.06.03.09:24:13 Info: fpga_interfaces: "hps" instantiated altera_interface_generator "fpga_interfaces"
     
144. 2015.06.03.09:24:14 Info: hps_io: "hps" instantiated altera_hps_io "hps_io"
     
145. 2015.06.03.09:24:14 Info: sys_description_rom: Starting RTL generation for module 'system_acl_iface_acl_kernel_interface_sys_description_rom'
     
146. 2015.06.03.09:24:14 Info: sys_description_rom:   Generation command is [exec G:/altera/quartus/bin64/perl/bin/perl.exe -I G:/altera/quartus/bin64/perl/lib -I G:/altera/quartus/sopc_builder/bin/europa -I G:/altera/quartus/sopc_builder/bin/perl_lib -I G:/altera/quartus/sopc_builder/bin -I G:/altera/quartus/../ip/altera/sopc_builder_ip/common -I G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=system_acl_iface_acl_kernel_interface_sys_description_rom --dir=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0017_sys_description_rom_gen/ --quartus_dir=G:/altera/quartus --verilog --config=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0017_sys_description_rom_gen//system_acl_iface_acl_kernel_interface_sys_description_rom_component_configuration.pl  --do_build_sim=0  ]
     
147. 2015.06.03.09:24:14 Info: sys_description_rom: Done RTL generation for module 'system_acl_iface_acl_kernel_interface_sys_description_rom'
     
148. 2015.06.03.09:24:14 Info: sys_description_rom: "acl_kernel_interface" instantiated altera_avalon_onchip_memory2 "sys_description_rom"
     
149. 2015.06.03.09:24:14 Info: mem_org_mode: "acl_kernel_interface" instantiated mem_org_mode "mem_org_mode"
     
150. 2015.06.03.09:24:14 Info: irq_bridge_0: "acl_kernel_interface" instantiated altera_irq_bridge "irq_bridge_0"
     
151. 2015.06.03.09:24:14 Info: irq_ena_0: "acl_kernel_interface" instantiated irq_ena "irq_ena_0"
     
152. 2015.06.03.09:24:14 Info: mm_interconnect_0: "acl_kernel_interface" instantiated altera_mm_interconnect "mm_interconnect_0"
     
153. 2015.06.03.09:24:16 Info: mm_interconnect_1: "acl_kernel_interface" instantiated altera_mm_interconnect "mm_interconnect_1"
     
154. 2015.06.03.09:24:16 Info: hps_h2f_lw_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_h2f_lw_axi_master_agent"
     
155. 2015.06.03.09:24:16 Info: version_id_s_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "version_id_s_agent"
     
156. 2015.06.03.09:24:16 Info: version_id_s_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "version_id_s_agent_rsp_fifo"
     
157. 2015.06.03.09:24:16 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
     
158. 2015.06.03.09:24:16 Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
     
159. 2015.06.03.09:24:16 Info: hps_h2f_lw_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_h2f_lw_axi_master_wr_limiter"
     
160. 2015.06.03.09:24:16 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_avalon_sc_fifo.v
     
161. 2015.06.03.09:24:17 Info: version_id_s_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "version_id_s_burst_adapter"
     
162. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_address_alignment.sv
     
163. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_avalon_st_pipeline_base.v
     
164. 2015.06.03.09:24:17 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
     
165. 2015.06.03.09:24:17 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
     
166. 2015.06.03.09:24:17 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
     
167. 2015.06.03.09:24:17 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
     
168. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
169. 2015.06.03.09:24:17 Info: address_span_extender_kernel_expanded_master_agent: "mm_interconnect_2" instantiated altera_merlin_master_agent "address_span_extender_kernel_expanded_master_agent"
     
170. 2015.06.03.09:24:17 Info: router: "mm_interconnect_2" instantiated altera_merlin_router "router"
     
171. 2015.06.03.09:24:17 Info: router_001: "mm_interconnect_2" instantiated altera_merlin_router "router_001"
     
172. 2015.06.03.09:24:17 Info: cmd_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux"
     
173. 2015.06.03.09:24:17 Info: cmd_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux"
     
174. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
175. 2015.06.03.09:24:17 Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux"
     
176. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
177. 2015.06.03.09:24:17 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
     
178. 2015.06.03.09:24:17 Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
     
179. 2015.06.03.09:24:17 Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
     
180. 2015.06.03.09:24:17 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
     
181. 2015.06.03.09:24:17 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
     
182. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
183. 2015.06.03.09:24:17 Info: cmd_mux_002: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002"
     
184. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
185. 2015.06.03.09:24:17 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
     
186. 2015.06.03.09:24:17 Info: rsp_demux_002: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_002"
     
187. 2015.06.03.09:24:17 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
     
188. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
189. 2015.06.03.09:24:17 Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
     
190. 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_avalon_st_pipeline_base.v
     
191. 2015.06.03.09:24:44 Info: border: "hps_io" instantiated altera_interface_generator "border"
     
192. 2015.06.03.09:24:44 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
     
193. 2015.06.03.09:24:44 Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
     
194. 2015.06.03.09:24:44 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
     
195. 2015.06.03.09:24:44 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
     
196. 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
197. 2015.06.03.09:24:44 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
     
198. 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
199. 2015.06.03.09:24:44 Info: kernel_cra_s0_cmd_width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "kernel_cra_s0_cmd_width_adapter"
     
200. 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_address_alignment.sv
     
201. 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv
     
202. 2015.06.03.09:24:44 Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
     
203. 2015.06.03.09:24:44 Info: router_001: "mm_interconnect_1" instantiated altera_merlin_router "router_001"
     
204. 2015.06.03.09:24:44 Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
     
205. 2015.06.03.09:24:44 Info: router_003: "mm_interconnect_1" instantiated altera_merlin_router "router_003"
     
206. 2015.06.03.09:24:44 Info: router_005: "mm_interconnect_1" instantiated altera_merlin_router "router_005"
     
207. 2015.06.03.09:24:44 Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
     
208. 2015.06.03.09:24:44 Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
     
209. 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
210. 2015.06.03.09:24:44 Info: cmd_mux_002: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_002"
     
211. 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
212. 2015.06.03.09:24:44 Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
     
213. 2015.06.03.09:24:44 Info: rsp_demux_002: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_002"
     
214. 2015.06.03.09:24:44 Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
     
215. 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv
     
216. 2015.06.03.09:24:44 Info: system: Done "system" with 85 modules, 199 files
     

复制代码

1696811157

zhaoyongke 发表于 2015-6-3 10:43
找到原因了，资源用爆了，建议用其他板子试试。

这板子可不是想换就换的。。。假如说资源用爆是电脑资源用爆还是DE1用爆

zhaoyongke

1696811157 发表于 2015-6-3 10:47
这板子可不是想换就换的。。。假如说资源用爆是电脑资源用爆还是DE1用爆

DE1板子资源很少的。报告显示DSP和LE资源都爆了。

1696811157

zhaoyongke 发表于 2015-6-3 10:48
DE1板子资源很少的。报告显示DSP和LE资源都爆了。

是不是该FFT处理数据过多，改少了应该可以吧。。。突发奇想

zhaoyongke

1696811157 发表于 2015-6-3 10:52
是不是该FFT处理数据过多，改少了应该可以吧。。。突发奇想

我刚刚改成256点FFT，LE会爆，DSP够用。现在改成64点试试。不过，FFT短了没有意义呀，工程中常用的还是1024，2048点以上的

1696811157

zhaoyongke 发表于 2015-6-3 11:49
我刚刚改成256点FFT，LE会爆，DSP够用。现在改成64点试试。不过，FFT短了没有意义呀，工程中常用的还是1024，2048点以上的

怎么改的，请赐教

1696811157

zhaoyongke 发表于 2015-6-3 11:49
我刚刚改成256点FFT，LE会爆，DSP够用。现在改成64点试试。不过，FFT短了没有意义呀，工程中常用的还是1024，2048点以上的

我的改成64的也不行呢，你的呢

1696811157

zhaoyongke 发表于 2015-6-3 11:49
我刚刚改成256点FFT，LE会爆，DSP够用。现在改成64点试试。不过，FFT短了没有意义呀，工程中常用的还是1024，2048点以上的

会不会是这个代码和de1不兼容呢？？？

zhaoyongke

1696811157 发表于 2015-6-3 19:17
会不会是这个代码和de1不兼容呢？？？

64也不行。找Altera人问问吧。

1696811157

zhaoyongke 发表于 2015-6-3 19:59
64也不行。找Altera人问问吧。

好的，谢谢了哈