从51转到cpld好象难度不大,这是我的第一个作品
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-- 闪动的led加数码管显示,还同学到数组使用,就先用一大堆IF,用case可能会稍好一点,但我还没有学会。
library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY My_Led IS
GENERIC(n:INteger:=20000000);
PORT
(
clk:IN std_logic; --系统时钟
dua:OUT std_logic_vector(7 DOWNTO 0);-- 数码管段
wei:OUT std_logic_vector(3 DOWNTO 0);-- 数码管位
d2,d3:OUT std_logic--两个led交替闪动
);
END My_Led;
ARCHITECTURE behave OF My_Led IS
SIGNAL tmp:std_logic;
SIGNAL cnt:INteger RANGE 0 to n;
SIGNAL nub:INteger RANGE 0 to 10;
BEGIN
PROCESS(clk) -- 这里是系统时钟相当于51的定时器
BEGIN
wei<="0111";
IF risINg_edge(clk) THEN
IF cnt>=n THEN
tmp<=not tmp;
cnt<=0;
nub<=nub + 1;
IF nub=10 THEN
nub<=0;
END IF;
IF nub= 0 THEN
dua<="00000011";
ELSIF nub=1 THEN
dua<="10011111";
ELSIF nub=2 THEN
dua<="00100101";
ELSIF nub=3 THEN
dua<="00001101";
ELSIF nub=4 THEN
dua<="10011001";
ELSIF nub=5 THEN
dua<="01001001";
ELSIF nub=6 THEN
dua<="01000001";
ELSIF nub=7 THEN
dua<="00011111";
ELSIF nub=8 THEN
dua<="00000001";
ELSIF nub=9 THEN
dua<="00001001";
END IF;
ELSE
cnt<=cnt + 1;
END IF;
d2<=tmp;
d3<=not tmp;
END IF;
END PROCESS;
END ARCHITECTURE;
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