请帮忙看看这段代码的错误在哪

瓷娃娃

请帮忙看看这段代码的错误在哪 [复制链接]

module example1(equal);
output equal;
reg a,b;
reg equal;
initial
begin
a=0;
b=0;

#100 a=0;b=1;
#100 b=1;b=1;
#100 a=1;b=0;
#100 $stop;
end
compare compare1(equal,a,b);
endmodule
module compare(equal,a,b);
        input a,b;
        output equal;
        assign equal=(a==b)?1:0;
endmodule

报错为：Error (10663): Verilog HDL Port Connection error at example1.v(47): output or inout port "equal" must be connected to a structural net expression

coyoo

compare compare1(equal,a,b);  这个调用是不是有点问题啊？