case语句用错了么？

shawn_ancy

case语句用错了么？ [复制链接]

module D_Metas(rst,key1,key2,key3,out_cw);
input rst,key1,key2,key3;
output [9:0] out_cw;

localparam
SHIW=10'b00_0000_0001,
SANW=10'b00_0000_1001,
WUW=10'b00_0001_0001,
QIW=10'b00_0101_0001;

reg [2:0] sel=3'b000;
reg fig=1;

always @(negedge rst) begin
fig=0;
end                                //reset sign


always @(negedge key1) begin
  if(fig)
     sel[0]=1;
  else
     sel[0]=0;
end


always @(negedge key2) begin
  if(fig)
     sel[1]=1;
  else
     sel[1]=0;
end


always @(negedge key3) begin
  if(fig)
     sel[2]=1;
  else
     sel[2]=0;
end


case(sel)
3'b100: begin out_cw=QIW; fig<=1; end
3'b010: begin out_cw=WUW; fig<=1; end
3'b001: begin out_cw=SANW; fig<=1; end
default: begin out_cw=SHIW; fig<=1; end
endcase

endmodule
提示错误：Error (10170): Verilog HDL syntax error at D_Metas.v(43) near text "case";  expecting "endmodule"

chenzhufly

你这个是时序电路？  还是组合电路？

jerrylwb

关注下，搞不懂这个语法错误

撼地神牛

规范定义一下变量，试试

mqliuttoong

把case语句用always语句包起来试试

tankejun

最后一个always中将IF和CASE语句用begin end 括起来就OK了