stm32定时器外部时钟源模式2与模式1的区别

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stm32定时器外部时钟源模式2与模式1的区别 [复制链接]

stm32定时器外部时钟源模式2与模式1的区别

安_然

External clock mode1 (TI1 or TI2 pins)
In this mode the external clock will be applied on timer input TI1 pin or TI2 pin. To do this:
1. Configure the timers to use the TIx pin as input:
a) Select the pin to be used by writing CCxS bits in the TIMx_CCMR1 register.
b) Select the polarity of the input:
For the STM32F10x family: by writing CCxP in the TIMx_CCER register to select
the rising or the falling edge;
For the other families: by writing CCxP and CCxNP in the TIMx_CCER register
to select the rising/falling edge, or both edges(a).

c) Configure the filter and the prescaler if needed by writing the ICxF[3:0] bits in the
TIMx_CCMR1:
Select the timer TIx as the trigger input source by writing TS bits in the
TIMx_SMCR register.
Select the external clock mode1 by writing SMS=111 in the TIMx_SMCR register.
Enable the corresponding channel by setting the CCEx bit in the TIMx_CCER
register.
2. Select the timer TIx as the trigger input source by writing TS bits in the TIMx_SMCR
register.
3. Select the external clock mode1 by writing SMS=111 in the TIMx_SMCR register.
External clock mode2 (ETR pin)
The external clock mode2 uses the ETR pin as timer input clock. To use this feature:
1. Select the external clock mode2 by writing ECE = 1 in the TIMx_SMCR register.
2. Configure, if needed, the prescaler, the filter and the polarity by writing ETPS [1:0], ETF
[3:0] and ETP in the TIMx_SMCR register.

Study_Stellaris

用 fwlib 吗？
具体指哪一项呢？

安_然

楼主请看如下说明，希望有所帮助：
The external clock timer is divided in two categories:
● External clock connected to TI1 or TI2 pins
● External clock connected to ETR pin
In these cases, the clock is provided by an external signal connected to TIx pins or ETR pin.
The maximum external clock frequency should be verified.
Note: 1 In addition to all these clock sources, the timer should be clocked with the APBx clock.
2 The external clocks are not directly feeding the prescaler, but they are first synchronized
with the APBx clock through dedicated logical blocks.