初学者求助一段VHDL代码

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初学者求助一段VHDL代码 [复制链接]

下面这段代码在quartus II中编译的时候提示语法错误，请问错在哪里？
library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity address3960 is

         port( CLOCK , RESET   : in std_logic ;

        address_data1  : out std_logic_vector(11 downto 0));

end address3960 ;

architecture rtl of address3960 is

signal CLK1  : std_logic ; -------------------------------internal_clock

signal count_f_counter : std_logic_vector(16 downto 0) ;

signal count_CLK: std_logic_vector(8 downto 0) ; -----------internal_signal_9bits

signal count_dat：std_logic_vector(11 downto 0) ;  -----------internal_signal_12bits

begin

---Counter----------------------------------------------------------------------------

process (CLOCK,RESET)

    begin

       if (RESET = '1') then

      count_CLK<="000000000"; --------------------------9bits_o

         CLK1 <= '0' ;      

       elsif (CLOCK'event and CLOCK = '1') then

         if (count_CLK< "111110011") then ------------------9bits_499

             count_CLK <= count_CLK + '1';

             clk1<='0';

elsif (count_CLK = "111110011" ) then --------------499

             count_CLK <= "000000000";

          clk1<='1';

         end if;

  end process;

---Calling_rom_address------------------------------------------------------------

process (CLK1,RESET)

    begin

       if (RESET = '1') then

     count_data1 <= "000000000000" ; ------------------------------8bits_0

      elsif (CLK1'event and CLK1 = '1') then

if (count_data1 < "111101110111") then -----------------------8bits_3959

       count_data1 <= count_data1 + '1';

  elsif (count_data1 = "111101110111" ) then -------------------8bits_3959

        count_data1 <= "000000000000";

            end if;

end if;

end process ;

         address_data1 <= count_data1 ;

end rtl;

流浪的猥琐

count_data1 没有声明，上面声明的是count_dat