library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.Std_logic_arith.all; use IEEE.Std_logic_unsigned.all;
-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity main is port(clk : in std_logic; dir : in std_logic_vector(3 downto 0); row : out std_logic_vector(7 downto 0); col : out std_logic_vector(7 downto 0); seven_1 : out std_logic_vector(6 downto 0)); end main;
architecture Behavioral of main is signal h1,l1,h2,l2,h3,l3,h4,l4,h6,l6 :integer range 0 to 7; signal row1 :std_logic_vector(0 to 7); signal col1 :std_logic_vector(0 to 7); signal count1 :std_logic_vector(9 downto 0):="0000000000"; signal count2 :std_logic_vector(3 downto 0):="0000"; signal count3 :std_logic_vector(3 downto 0):="0000"; signal seven :std_logic_vector(6 downto 0); signal six :std_logic_vector(5 downto 0); signal c :integer range 0 to 4; signal dir1 :std_logic_vector(1 downto 0);
begin process(clk) begin if clk = '1' and clk'Event then count1<=count1+1; end if; end process;
process(count1(9)) begin if count1(9)='1' and count1(9)'Event then count3<=count3+1; end if; end process;
process(count1(8)) begin if count1(8)='1' and count1(8)'Event then if h1=h6 and l1=l6 then h6<=h6+2; l6<=l6+1; count2<=count2+1; end if; h4<=h3; l4<=l3; h3<=h2; l3<=l2; h2<=h1; l2<=l1; case dir is when"1000"=>if(dir1/="10")then if l1=7 then l1<=0; else l1<=l1+1; end if; dir1<="00"; else l1<=l1-1; end if; when"0100"=>if(dir1/="11")then if(h1=0)then h1<=7; else h1<=h1-1; end if; dir1<="01"; else h1<=h1+1; end if; when"0010"=>if(dir1/="00")then if(l1=0)then l1<=7; else l1<=l1-1; end if; dir1<="10"; else l1<=l1+1; end if; when"0001"=>if(dir1/="01")then if(h1=7)then h1<=0; else h1<=h1+1; end if; dir1<="11"; else h1<=h1-1; end if; when others=>case dir1 is when"00"=>if(l1=7)then l1<=0; else l1<=l1+1; end if; when"01"=>if(h1=0)then h1<=7; else h1<=h1-1; end if; when"10"=>if(l1=0)then l1<=7; else l1<=l1-1; end if; when"11"=>if(h1=7)then h1<=0; else h1<=h1+1; end if; when others=>Null; end case; end case; end if; end process; process(clk) begin if clk'Event and clk='1' then row1<="00000000"; col1<="11111111"; if(c=4)then c<=0; else c<=c+1; end if; case c is when 1=>row1(h1)<='1'; col1(l1)<='0'; when 2=>row1(h2)<='1'; col1(l2)<='0'; case count2 is when"0000"=>seven<="1111110"; when"0001"=>seven<="0110000"; when"0010"=>seven<="1101101"; when"0011"=>seven<="1111001"; when"0100"=>seven<="0110011"; when"0101"=>seven<="1011011"; when"0110"=>seven<="1011111"; when"0111"=>seven<="1110000"; when"1000"=>seven<="1111111"; when"1001"=>seven<="1111011"; when others=>seven<="1111111"; end case; when 3=>row1(h3)<='1'; col1(l3)<='0'; case count3 is when"0000"=>seven<="1111110"; when"0001"=>seven<="1000111"; when"0010"=>seven<="1001111"; when"0011"=>seven<="0111101"; when"0100"=>seven<="1001110"; when"0101"=>seven<="0011111"; when"0110"=>seven<="1110111"; when"0111"=>seven<="1111011"; when"1000"=>seven<="1111111"; when"1001"=>seven<="1110000"; when"1010"=>seven<="1011111"; when"1011"=>seven<="1011011"; when"1100"=>seven<="0110011"; when"1101"=>seven<="1111001"; when"1110"=>seven<="1101101"; when"1111"=>seven<="0110000"; when others=>seven<="1111111"; end case; when 4=>row1(h4)<='1'; col1(l4)<='0'; when 0=>row1(h6)<='1'; col1(l6)<='0'; end case; end if; end process; row<=row1; col<=col1; seven_1<=seven;
end Behavioral; —————————————————————————————————————————————————————————————————————— 前面都能看懂是关于控制蛇运动和食物隐现的代码,问题是后面在vga显示器上显示这段有些糊涂了 if clk'Event and clk='1' then
row1<="00000000";
col1<="11111111";
if(c=4)then
c<=0;
else
c<=c+1;
end if;
case c is
when 1=>row1(h1)<='1';
col1(l1)<='0';
when 2=>row1(h2)<='1';
col1(l2)<='0'; 这段到底是什么意思,希望各位大侠能帮忙解释一下,另外还想请教这个程序的col和row的ucf到底该怎么写,谢谢(是在Nexys3板子上跑的)