求教 如何修改程序把英文字符显示修改为汉字显示

小贾

求教 如何修改程序把英文字符显示修改为汉字显示 [复制链接]

这是基于FPGA的LCD控制器的设计与实现  要求实现英文字符和汉字  字符没问题  汉字也知道

中文部分的实现原理与英文部分大体相同，但是由于VHDL中无法识别中文，因此在使用上不可能做到和英文一样方便。使用时需要参照中文字符表，将需要的字符所对应的数据输入RAM，然后通和英文模块不重复的符号来实现对其的调用。如 “贾”这个中文字符，所对应的数据为16#BCD6，因此在函数部分应为：

    when '@' => result := 16#BC#;

    when '#' => result := 16#D6#;

调用时的只需将@和#这两个符号来代替中文字符即可

when "000000" =>data<=conv_std_logic_vector (char_to_integer ('@'),8);

when "000001" =>data<=conv_std_logic_vector (char_to_integer ('#'),8)；

 

但是还是遇到问题了，求指教：

附字符显示的VHDL程序（已经调试 没问题）

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
  package packexp is
      function char_to_integer(indata : character) return integer ;
   end;
   package BODY packexp is
     function char_to_integer(indata : character) return integer is
        variable result : integer range 0 to 16#FF#;
       begin
     case indata is
     when ' ' => result := 16#20#;
     when '!' => result := 16#21#;
     when '.' => result := 16#2E#;
     when ':' => result := 16#3A#;
     when 'a' => result := 16#61#;
     when 'b' => result := 16#62#;
     when 'c' => result := 16#63#;
     when 'd' => result := 16#64#;
     when 'e' => result := 16#65#;
     when 'f' => result := 16#66#;
     when 'g' => result := 16#67#;
     when 'h' => result := 16#68#;
     when 'i' => result := 16#69#;
     when 'j' => result := 16#6A#;
     when 'k' => result := 16#6B#;
     when 'l' => result := 16#6C#;
     when 'm' => result := 16#6D#;
     when 'n' => result := 16#6E#;
     when 'o' => result := 16#6F#;
     when 'p' => result := 16#70#;
     when 'q' => result := 16#71#;
     when 'r' => result := 16#72#;
     when 's' => result := 16#73#;
     when 't' => result := 16#74#;
     when 'u' => result := 16#75#;
     when 'v' => result := 16#76#;
     when 'w' => result := 16#77#;
     when 'x' => result := 16#78#;
     when 'y' => result := 16#79#;
     when 'z' => result := 16#7A#;
     when 'A' => result := 16#41#;
     when 'B' => result := 16#42#;
     when 'C' => result := 16#43#;
     when 'D' => result := 16#44#;
     when 'E' => result := 16#45#;
     when 'F' => result := 16#46#;
     when 'G' => result := 16#47#;
     when 'H' => result := 16#48#;
     when 'I' => result := 16#49#;
     when 'J' => result := 16#4A#;
     when 'K' => result := 16#4B#;
     when 'L' => result := 16#4C#;
     when 'M' => result := 16#4D#;
     when 'N' => result := 16#4E#;
     when 'O' => result := 16#4F#;
     when 'P' => result := 16#50#;
     when 'Q' => result := 16#51#;
     when 'R' => result := 16#52#;
     when 'S' => result := 16#53#;
     when 'T' => result := 16#54#;
     when 'U' => result := 16#55#;
     when 'V' => result := 16#56#;
     when 'W' => result := 16#57#;
     when 'X' => result := 16#58#;
     when 'Y' => result := 16#59#;
     when 'Z' => result := 16#5A#;
     when '0' => result := 16#30#;
     when '1' => result := 16#31#;
     when '2' => result := 16#32#;
     when '3' => result := 16#33#;
     when '4' => result := 16#34#;
     when '5' => result := 16#35#;
     when '6' => result := 16#36#;
     when '7' => result := 16#37#; 
     when '8' => result := 16#38#;
     when '9' => result := 16#39#;
     when others => result := 16#20#;
     end case;
     return result;
    end function;  
  end;
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use work.packexp.all;
  entity YWZF is
     port ( clk : in std_logic;
  address : in std_logic_vector(5 downto 0);
  data: out std_logic_vector(7 downto 0) );
    end YWZF;
  architecture C of YWZF is
     begin
      process(clk,address)
         begin
  if clk'event and clk='1' then
       case address is
     when "000000" =>data<=conv_std_logic_vector (char_to_integer ('H'),8);
     when "000001" =>data<=conv_std_logic_vector (char_to_integer ('a'),8);
     when "000010" =>data<=conv_std_logic_vector (char_to_integer ('p'),8);
     when "000011" =>data<=conv_std_logic_vector (char_to_integer ('p'),8);
     when "000100" =>data<=conv_std_logic_vector (char_to_integer ('y'),8);
     when "000101" =>data<=conv_std_logic_vector (char_to_integer (' '),8);
     when "000110" =>data<=conv_std_logic_vector (char_to_integer ('b'),8);
     when "000111" =>data<=conv_std_logic_vector (char_to_integer ('i'),8);
     when "001000" =>data<=conv_std_logic_vector (char_to_integer ('r'),8);
     when "001001" =>data<=conv_std_logic_vector (char_to_integer ('t'),8);
     when "001010" =>data<=conv_std_logic_vector (char_to_integer ('h'),8);
     when "001011" =>data<=conv_std_logic_vector (char_to_integer ('d'),8);
     when "001100" =>data<=conv_std_logic_vector (char_to_integer ('a'),8);
     when "001101" =>data<=conv_std_logic_vector (char_to_integer ('y'),8);
     when "001110" =>data<=conv_std_logic_vector (char_to_integer (' '),8);
     when "001111" =>data<=conv_std_logic_vector (char_to_integer ('t'),8);
     when "010000" =>data<=conv_std_logic_vector (char_to_integer ('o'),8);
     when "010001" =>data<=conv_std_logic_vector (char_to_integer (' '),8);
     when "010010" =>data<=conv_std_logic_vector (char_to_integer ('u'),8);
     when "010011" =>data<=conv_std_logic_vector (char_to_integer (' '),8);
     when "010100" =>data<=conv_std_logic_vector (char_to_integer ('!'),8);
        when others =>data<=conv_std_logic_vector (char_to_integer (' '),8);
     end case;  
 end if;
 end process; 
  end C;

 

新手急求！

 

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啥问题？