VHDL语言编写ADC0809数字电压表转换程序

博雷德

VHDL语言编写ADC0809数字电压表转换程序 [复制链接]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ad_hgq is
  port(
        d :in std_logic_vector(7 downto 0);---AD输入；
        clk,eoc :in std_logic; ---eoc:转换结束状态信号；
 oe : buffer std_logic; 
        ale,start:out std_logic; ---ale:允许地址锁存；
        q :buffer std_logic_vector(7 downto 0);
        OneUSCLK : inout std_logic
    ); ---转换数据输出显示；       
end ad_hgq;
architecture behaviour of ad_hgq is
  type state is (st0,st1,st2,st3,st4,st5,st6,st7); ---以枚举类型定义各状态子类型；
  signal current_state,next_state :state:=st0;  
  signal regl :std_logic_vector(7 downto 0);
  signal lock :std_logic;           ---转换后数据输出锁存时钟信号；
  signal hex :std_logic_vector(7 downto 0);
  signal clkCount: std_logic_vector (6 downto 0);
 begin
process(current_state,eoc)
begin
case current_state is
    when st0=> ale<='0';start<='0';oe<='0';lock<='0'; next_state<=st1;
                   ---初始态ST0向下一状态ST1转换,0809采样控制信号初始化；
    when st1=> ale<='1';start<='0';oe<='0';lock<='0'; next_state<=st2;
                   ---由ALE的上升沿将通道地址'001'锁入0809的地址寄存器；
    when st2=> ale<='1';start<='1';oe<='0';lock<='0'; next_state<=st3;  ---启动采样信号；
    when st3=> ale<='0';start<='1';oe<='0';lock<='0';
      if(eoc='0')  then  next_state<=st4; ---转换即将结束,转换至下一状态；
        else next_state<=st3;   ---转换未结束,继续在状态ST3中等待；
      end if;
    when st4=> ale<='0';start<='0';oe<='0';lock<='0';
      if(eoc='1')  then  next_state<=st5; ---EOC由0恢复1,转换结束；
        else next_state<=st4; ---转换未结束,等待；
      end if;
    when st5=> ale<='0';start<='0';oe<='1';lock<='0'; next_state<=st6;  --开启输出允许OE；
    when st6=> ale<='0';start<='0';oe<='1';lock<='1'; next_state<=st7;  --开启数据锁存LOCK；
    when st7=> ale<='0';start<='0';oe<='0';lock<='1'; next_state<=st0;
    when others=>next_state<=st0;  ---其它状态返回ST0；
  end case;
  end process;
process (CLK)
     begin
  if (CLK = '1' and CLK'event) then
   if(clkCount = "1100011") then
    clkCount <= "0000000";
    oneUSClk <= not oneUSClk;
   else
    clkCount <= clkCount + 1;
   end if;
  end if;
 end process;
process(oneUSClk)
  begin
    if(oneUSClk'event and oneUSClk='1')  then  current_state<=next_state;
    end if;     ---在时钟上升沿,转换至下一状态；
end process ; ---由信号current_state将当前状态带出进程,进入下一进程；
process(lock)
  begin
    if (lock='1'and lock'event)  then  regl<=d;
    end if; --在lock上升沿,将转换好的数据锁存入8位锁存器中；
end process; 
q<=regl; ---数据输出；
process(oneUSClk)
  begin
    if( oneUSClk'event and oneUSClk ='1')  then  if oe='1'  then  hex<=q; ---将数据送给hex；
      end if;
    end if;
end process;  
end behaviour;

eeleader

不错，好东西，我收下！