testbench:
reg inclk0; reg rst; wire c0; //wire c1;
// assign statements (if any) din10 i1 ( // port map - connection between master ports and signals/registers .c0(c0), //.c1(c1), .inclk0(inclk0), .rst(rst) ); initial begin inclk0=0; rst=0; #5 rst=1; end always #5 inclk0=~inclk0; endmodule
代码:
module din10(rst,inclk0,c0); input rst,inclk0; output c0; reg c0; //reg [3:0] cnt; //assign c1=inclk0; //assign c0= cnt[2] ? 1:0; always @(posedge inclk0) if(!rst) c0=0; //cnt<=4'b0; else begin //cnt=cnt+1; //c1= cnt[0]; //c0 =cnt[3]; c0=~c0; end endmodule
为什么modelsim仿真出不来 c0
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