assign sine=sine_dr;
assign ROM_A=ADD_B[31:22];//
always@(posedge clk or posedge reset) //enabe SYSTEM
begin
if(reset)
ADD_A<=0;
else if(we)
ADD_A<=data;
end
always@(posedge clk or posedge reset) //enable dds
begin
if(reset)
ADD_B<=0;
else if(ce)
ADD_B<=ADD_B+ADD_A;///
end
always@(posedge clk or posedge reset)
begin
if(reset)
sine_dr<=0;
else if(ce)
sine_dr<=sine_d;
end
rom_sine sine1(.addr(ROM_A),.clk(clk),.dout(sine_d));
endmodule