VHDL 中的PACKAGE 定义:
package n_bit_int is ---用户定义类型
subtype bit15 is integer -2**14 to 2**14-1;---(-2^14 to 2^14-1)
end n_bit_int;
利用上面的声明,实现IIR滤波的递推公式:
y(n+1)=3/4 * y(n)+x(n);
library work
use .work.n_bit_int.all;
library ieee;
use.ieee.std_logic_1164.all;
use.ieee.std_logic_arith.all;
entity iirfilter is
port
(clk:in std_logic;
x_in:in bit15;
y_out:out bit15
);
end iirfilter;
architecture iir of iirfilter is
signal x,y:bit15;
begin
process
wait until clk='1';
x<=x_in;
y<=x+y/4+y/2;
end process;
y_out<=y;
end iir;
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