LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY freq IS
PORT(
BCLK:IN STD_LOGIC;--标准频率信号
TCLK:IN STD_LOGIC;--待测频率信号
CL:IN STD_LOGIC;--
CLR:IN STD_LOGIC; --清零和初始化信号
START:OUT STD_LOGIC;--有低电平变到高电平时指示计数结束
SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);--两个32位计数器值分8位读出多路选择器
DATA:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--8位数据读出
);
END ENTITY freq;
ARCHITECTURE behav OF freq IS
SIGNAL BZQ:STD_LOGIC_VECTOR(31 DOWNTO 0);--标准计数器
SIGNAL TSQ:STD_LOGIC_VECTOR(31 DOWNTO 0);--被测频率计数
SIGNAL ENA:STD_LOGIC;--计数使能
-- SIGNAL BCLK:STD_LOGIC;
-- SIGNAL BENA,PUL:STD_LOGIC;--脉宽计数使能
--SIGNAL SS:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
START<=ENA;
DATA<=BZQ(7 DOWNTO 0) WHEN SEL="000"ELSE --标准频率计数低8位输出
BZQ(15 DOWNTO 8) WHEN SEL="001"ELSE
BZQ(23 DOWNTO 16)WHEN SEL="010"ELSE
BZQ(31 DOWNTO 24)WHEN SEL="011"ELSE
TSQ(7 DOWNTO 0) WHEN SEL="100"ELSE --被测频率计数低8位输出
TSQ(15 DOWNTO 8) WHEN SEL="101"ELSE
TSQ(23 DOWNTO 16)WHEN SEL="110"ELSE
TSQ(31 DOWNTO 24)WHEN SEL="111"ELSE
TSQ(31 DOWNTO 24);
BZH:PROCESS(BCLK,CLR,ENA) --标准频率测试计数器,标准计数器
BEGIN
IF CLR='0'THEN
BZQ<=(OTHERS=>'0');
ELSIF BCLK'EVENT AND BCLK='1'THEN
IF ENA='1'THEN
BZQ<=BZQ+1;
END IF;
END IF;
END PROCESS;
TF:PROCESS(TCLK,CLR,ENA) --待测频率计数,频率计数器
BEGIN
IF CLR='0'THEN
TSQ<=(OTHERS=>'0');
ELSIF TCLK'EVENT AND TCLK='1'THEN
IF ENA='1'THEN
TSQ<=TSQ+1;
END IF;
END IF;
END PROCESS;
PROCESS(TCLK,CLR) --计数控制使能触发器,CL为预置门控信号
BEGIN
IF CLR='0'THEN
ENA<='0';
ELSIF TCLK'EVENT AND TCLK='1'THEN
ENA<=CL;
END IF;
END PROCESS;
END ARCHITECTURE behav;